Sensor Fusion Library 0.6.1
Orientation sensing for Espressif (ESP32, ESP8266) processors
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driver_fxas21002.h
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1/*
2 * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
14#ifndef DRIVER_FXAS21002_H_
15#define DRIVER_FXAS21002_H_
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
25enum {
26 FXAS21002_STATUS = 0x00,
27 FXAS21002_OUT_X_MSB = 0x01,
28 FXAS21002_OUT_X_LSB = 0x02,
29 FXAS21002_OUT_Y_MSB = 0x03,
30 FXAS21002_OUT_Y_LSB = 0x04,
31 FXAS21002_OUT_Z_MSB = 0x05,
32 FXAS21002_OUT_Z_LSB = 0x06,
33 FXAS21002_DR_STATUS = 0x07,
34 FXAS21002_F_STATUS = 0x08,
35 FXAS21002_F_SETUP = 0x09,
36 FXAS21002_F_EVENT = 0x0A,
37 FXAS21002_INT_SRC_FLAG = 0x0B,
38 FXAS21002_WHO_AM_I = 0x0C,
39 FXAS21002_CTRL_REG0 = 0x0D,
40 FXAS21002_RT_CFG = 0x0E,
41 FXAS21002_RT_SRC = 0x0F,
42 FXAS21002_RT_THS = 0x10,
43 FXAS21002_RT_COUNT = 0x11,
44 FXAS21002_TEMP = 0x12,
45 FXAS21002_CTRL_REG1 = 0x13,
46 FXAS21002_CTRL_REG2 = 0x14,
47 FXAS21002_CTRL_REG3 = 0x15,
48};
49
50
51/*--------------------------------
52** Register: STATUS
53** Enum: FXAS21002_STATUS
54** --
55** Offset : 0x00 - Alias for DR_STATUS or F_STATUS.
56** ------------------------------*/
57typedef uint8_t FXAS21002_STATUS_t;
58
59
60
61/*--------------------------------
62** Register: OUT_X_MSB
63** Enum: FXAS21002_OUT_X_MSB
64** --
65** Offset : 0x01 - 8 MSBs of 16 bit X-axis data sample
66** ------------------------------*/
67typedef uint8_t FXAS21002_OUT_X_MSB_t;
68
69
70/*--------------------------------
71** Register: OUT_X_LSB
72** Enum: FXAS21002_OUT_X_LSB
73** --
74** Offset : 0x02 - 8 LSBs of 16 bit X-axis data sample
75** ------------------------------*/
76typedef uint8_t FXAS21002_OUT_X_LSB_t;
77
78
79
80/*--------------------------------
81** Register: OUT_Y_MSB
82** Enum: FXAS21002_OUT_Y_MSB
83** --
84** Offset : 0x03 - 8 MSBs of 16 bit Y-axis data sample
85** ------------------------------*/
86typedef uint8_t FXAS21002_OUT_Y_MSB_t;
87
88
89/*--------------------------------
90** Register: OUT_Y_LSB
91** Enum: FXAS21002_OUT_Y_LSB
92** --
93** Offset : 0x04 - 8 LSBs of 16 bit Y-axis data sample
94** ------------------------------*/
95typedef uint8_t FXAS21002_OUT_Y_LSB_t;
96
97
98
99/*--------------------------------
100** Register: OUT_Z_MSB
101** Enum: FXAS21002_OUT_Z_MSB
102** --
103** Offset : 0x05 - 8 MSBs of 16 bit Z-axis data sample
104** ------------------------------*/
105typedef uint8_t FXAS21002_OUT_Z_MSB_t;
106
107
108/*--------------------------------
109** Register: OUT_Z_LSB
110** Enum: FXAS21002_OUT_Z_LSB
111** --
112** Offset : 0x06 - 8 LSBs of 16 bit Z-axis data sample
113** ------------------------------*/
114typedef uint8_t FXAS21002_OUT_Z_LSB_t;
115
116
117
118/*--------------------------------
119** Register: DR_STATUS
120** Enum: FXAS21002_DR_STATUS
121** --
122** Offset : 0x07 - Data-ready status information (FIFO disabled by setting F_SETUP :: F_MODE = 0)
123** ------------------------------*/
124typedef union {
125 struct {
126 uint8_t xdr : 1; /* X-axis new data available. */
127
128 uint8_t ydr : 1; /* Y-axis new data available. */
129
130 uint8_t zdr : 1; /* Z-axis new data available. */
131
132 uint8_t zyxdr : 1; /* X-, Y-, and Z-axis data available. */
133
134 uint8_t xow : 1; /* X-axis data overwrite. */
135
136 uint8_t yow : 1; /* Y-axis data overwrite. */
137
138 uint8_t zow : 1; /* Z-axis data overwrite. */
139
140 uint8_t zyxow : 1; /* X-, Y-, Z-axis data overwrite. */
141
142 } b;
143 uint8_t w;
144} FXAS21002_DR_STATUS_t;
145
146
147/*
148** DR_STATUS - Bit field mask definitions
149*/
150#define FXAS21002_DR_STATUS_XDR_MASK ((uint8_t) 0x01)
151#define FXAS21002_DR_STATUS_XDR_SHIFT ((uint8_t) 0)
152
153#define FXAS21002_DR_STATUS_YDR_MASK ((uint8_t) 0x02)
154#define FXAS21002_DR_STATUS_YDR_SHIFT ((uint8_t) 1)
155
156#define FXAS21002_DR_STATUS_ZDR_MASK ((uint8_t) 0x04)
157#define FXAS21002_DR_STATUS_ZDR_SHIFT ((uint8_t) 2)
158
159#define FXAS21002_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
160#define FXAS21002_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
161
162#define FXAS21002_DR_STATUS_XOW_MASK ((uint8_t) 0x10)
163#define FXAS21002_DR_STATUS_XOW_SHIFT ((uint8_t) 4)
164
165#define FXAS21002_DR_STATUS_YOW_MASK ((uint8_t) 0x20)
166#define FXAS21002_DR_STATUS_YOW_SHIFT ((uint8_t) 5)
167
168#define FXAS21002_DR_STATUS_ZOW_MASK ((uint8_t) 0x40)
169#define FXAS21002_DR_STATUS_ZOW_SHIFT ((uint8_t) 6)
170
171#define FXAS21002_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
172#define FXAS21002_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
173
174
175/*
176** DR_STATUS - Bit field value definitions
177*/
178#define FXAS21002_DR_STATUS_XDR_DRDY ((uint8_t) 0x01) /* Set to 1 whenever a new X-axis data acquisition */
179 /* is completed. Cleared anytime the OUT_X_MSB */
180 /* register is read. */
181#define FXAS21002_DR_STATUS_YDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a new Y-axis data acquisition */
182 /* is completed. Cleared anytime the OUT_Y_MSB */
183 /* register is read. */
184#define FXAS21002_DR_STATUS_ZDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Z-axis data acquisition */
185 /* is completed. Cleared anytime the OUT_Z_MSB */
186 /* register is read. */
187#define FXAS21002_DR_STATUS_ZYXDR_DRDY ((uint8_t) 0x08) /* Cleared when the high-bytes of the acceleration */
188 /* data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. */
189#define FXAS21002_DR_STATUS_XOW_OWR ((uint8_t) 0x10) /* Asserted whenever a new X-axis acquisition is */
190 /* completed before the retrieval of the previous */
191 /* data. */
192#define FXAS21002_DR_STATUS_YOW_OWR ((uint8_t) 0x20) /* Asserted whenever a new Y-axis acquisition is */
193 /* completed before the retrieval of the previous */
194 /* data. */
195#define FXAS21002_DR_STATUS_ZOW_OWR ((uint8_t) 0x40) /* Asserted whenever a new Z-axis acquisition is */
196 /* completed before the retrieval of the previous */
197 /* data. */
198#define FXAS21002_DR_STATUS_ZYXOW_OWR ((uint8_t) 0x80) /* Asserted whenever new X-, Y-, and Z-axis data is */
199 /* acquired before completing the retrieval of the */
200 /* previous set. */
201/*------------------------------*/
202
203
204
205/*--------------------------------
206** Register: F_STATUS
207** Enum: FXAS21002_F_STATUS
208** --
209** Offset : 0x08 - FIFO status information (FIFO enabled by setting F_SETUP :: F_MODE > 0)
210** ------------------------------*/
211typedef union {
212 struct {
213 uint8_t f_cnt : 6; /* FIFO sample counter; indicates the number of samples currently stored in */
214 /* the FIFO. */
215
216 uint8_t f_wmkf : 1; /* FIFO sample count greater than or equal to the watermark count (F_SETUP :: */
217 /* F_WMRK) has been detected. */
218
219 uint8_t f_ovf : 1; /* FIFO overflow event, such as when F_CNT = 32 and a new sample arrives, */
220 /* asserts the F_OVF flag. */
221
222 } b;
223 uint8_t w;
224} FXAS21002_F_STATUS_t;
225
226
227/*
228** F_STATUS - Bit field mask definitions
229*/
230#define FXAS21002_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
231#define FXAS21002_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
232
233#define FXAS21002_F_STATUS_F_WMKF_MASK ((uint8_t) 0x40)
234#define FXAS21002_F_STATUS_F_WMKF_SHIFT ((uint8_t) 6)
235
236#define FXAS21002_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
237#define FXAS21002_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
238
239
240/*
241** F_STATUS - Bit field value definitions
242*/
243#define FXAS21002_F_STATUS_F_WMKF_DETECT ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */
244#define FXAS21002_F_STATUS_F_OVF_DETECT ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */
245/*------------------------------*/
246
247
248
249/*--------------------------------
250** Register: F_SETUP
251** Enum: FXAS21002_F_SETUP
252** --
253** Offset : 0x09 - FIFO configuration
254** ------------------------------*/
255typedef union {
256 struct {
257 uint8_t f_wmrk : 6; /* FIFO operating mode selection. */
258
259 uint8_t f_mode : 2; /* FIFO sample count watermark setting. */
260
261 } b;
262 uint8_t w;
263} FXAS21002_F_SETUP_t;
264
265
266/*
267** F_SETUP - Bit field mask definitions
268*/
269#define FXAS21002_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
270#define FXAS21002_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
271
272#define FXAS21002_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
273#define FXAS21002_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
274
275
276/*
277** F_SETUP - Bit field value definitions
278*/
279#define FXAS21002_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */
280#define FXAS21002_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO is in Circular Buffer mode. */
281#define FXAS21002_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO is in Stop mode. */
282/*------------------------------*/
283
284
285
286/*--------------------------------
287** Register: F_EVENT
288** Enum: FXAS21002_F_EVENT
289** --
290** Offset : 0x0A - FIFO event status
291** ------------------------------*/
292typedef union {
293 struct {
294 uint8_t fe_time : 5; /* Number of ODR periods elapsed since F_EVENT was set. */
295
296 uint8_t f_event : 1; /* FIFO Event: Indicates if either F_WMKF or F_OVF flags are set (logical */
297 /* OR). */
298
299 } b;
300 uint8_t w;
301} FXAS21002_F_EVENT_t;
302
303
304/*
305** F_EVENT - Bit field mask definitions
306*/
307#define FXAS21002_F_EVENT_FE_TIME_MASK ((uint8_t) 0x1F)
308#define FXAS21002_F_EVENT_FE_TIME_SHIFT ((uint8_t) 0)
309
310#define FXAS21002_F_EVENT_F_EVENT_MASK ((uint8_t) 0x20)
311#define FXAS21002_F_EVENT_F_EVENT_SHIFT ((uint8_t) 5)
312
313
314/*
315** F_EVENT - Bit field value definitions
316*/
317#define FXAS21002_F_EVENT_F_EVENT_DETECTED ((uint8_t) 0x20) /* FIFO event was detected */
318/*------------------------------*/
319
320
321
322/*--------------------------------
323** Register: INT_SRC_FLAG
324** Enum: FXAS21002_INT_SRC_FLAG
325** --
326** Offset : 0x0B - Interrupt source status
327** ------------------------------*/
328typedef union {
329 struct {
330 uint8_t src_drdy : 1; /* Data ready event source flag. */
331
332 uint8_t src_rt : 1; /* Rate threshold event source flag. */
333
334 uint8_t src_fifo : 1; /* FIFO event source flag. */
335
336 uint8_t bootend : 1; /* Boot sequence complete event flag. */
337
338 } b;
339 uint8_t w;
340} FXAS21002_INT_SRC_FLAG_t;
341
342
343/*
344** INT_SRC_FLAG - Bit field mask definitions
345*/
346#define FXAS21002_INT_SRC_FLAG_SRC_DRDY_MASK ((uint8_t) 0x01)
347#define FXAS21002_INT_SRC_FLAG_SRC_DRDY_SHIFT ((uint8_t) 0)
348
349#define FXAS21002_INT_SRC_FLAG_SRC_RT_MASK ((uint8_t) 0x02)
350#define FXAS21002_INT_SRC_FLAG_SRC_RT_SHIFT ((uint8_t) 1)
351
352#define FXAS21002_INT_SRC_FLAG_SRC_FIFO_MASK ((uint8_t) 0x04)
353#define FXAS21002_INT_SRC_FLAG_SRC_FIFO_SHIFT ((uint8_t) 2)
354
355#define FXAS21002_INT_SRC_FLAG_BOOTEND_MASK ((uint8_t) 0x08)
356#define FXAS21002_INT_SRC_FLAG_BOOTEND_SHIFT ((uint8_t) 3)
357
358
359/*
360** INT_SRC_FLAG - Bit field value definitions
361*/
362#define FXAS21002_INT_SRC_FLAG_SRC_DRDY_READY ((uint8_t) 0x01) /* Asserted whenever a data-ready event triggers */
363 /* the interrupt. */
364#define FXAS21002_INT_SRC_FLAG_SRC_RT_THRESH ((uint8_t) 0x02) /* Indicates that the rate threshold event flag */
365 /* triggered the interrupt. */
366#define FXAS21002_INT_SRC_FLAG_SRC_FIFO_EVENT ((uint8_t) 0x04) /* F_OVF or F_WMKF are set, provided the FIFO */
367 /* interrupt is enabled. */
368#define FXAS21002_INT_SRC_FLAG_BOOTEND_BOOT_DONE ((uint8_t) 0x08) /* Boot sequence is complete. */
369/*------------------------------*/
370
371
372
373/*--------------------------------
374** Register: WHO_AM_I
375** Enum: FXAS21002_WHO_AM_I
376** --
377** Offset : 0x0C - The WHO_AM_I register contains the device idenifier.
378** ------------------------------*/
379typedef union {
380 struct {
381 uint8_t whoami; /* The WHO_AM_I register contains the device identifier which is factory */
382 /* programmed. */
383
384 } b;
385 uint8_t w;
386} FXAS21002_WHO_AM_I_t;
387
388
389/*
390** WHO_AM_I - Bit field mask definitions
391*/
392#define FXAS21002_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF)
393#define FXAS21002_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0)
394
395
396/*
397** WHO_AM_I - Bit field value definitions
398*/
399#define FXAS21002_WHO_AM_I_WHOAMI_OLD_VALUE ((uint8_t) 0xd1) /* FXAS21000 */
400#define FXAS21002_WHO_AM_I_WHOAMI_PRE_VALUE ((uint8_t) 0xd6) /* Engineering Samples */
401#define FXAS21002_WHO_AM_I_WHOAMI_PROD_VALUE ((uint8_t) 0xd7) /* FXAS21002 Rev 2.1 (production) */
402/*------------------------------*/
403
404
405
406/*--------------------------------
407** Register: CTRL_REG0
408** --
409** Offset : 0x0D - Used for general control and configuration.
410** ------------------------------*/
411typedef union {
412 struct {
413 uint8_t fs : 2; /* Full-scale range selection. */
414
415 uint8_t hpf_en : 1; /* High-pass filter enable. The high-pass filter is initialized on operating */
416 /* mode and ODR change. When enabled, the HPF is applied to the angular rate */
417 /* data supplied to the output registers/FIFO and the embedded rate threshold */
418 /* algorithm. */
419
420 uint8_t sel : 2; /* High-pass filter cutoff frequency selection. */
421
422 uint8_t spiw : 1; /* SPI interface mode selection. */
423
424 uint8_t bw : 2; /* Bandwidth selects the cut-off frequency of the digital low-pass filter. */
425
426 } b;
427 uint8_t w;
428} FXAS21002_CTRL_REG0_t;
429
430
431/*
432** CTRL_REG0 - Bit field mask definitions
433*/
434#define FXAS21002_CTRL_REG0_FS_MASK ((uint8_t) 0x03)
435#define FXAS21002_CTRL_REG0_FS_SHIFT ((uint8_t) 0)
436
437#define FXAS21002_CTRL_REG0_HPF_EN_MASK ((uint8_t) 0x04)
438#define FXAS21002_CTRL_REG0_HPF_EN_SHIFT ((uint8_t) 2)
439
440#define FXAS21002_CTRL_REG0_SEL_MASK ((uint8_t) 0x18)
441#define FXAS21002_CTRL_REG0_SEL_SHIFT ((uint8_t) 3)
442
443#define FXAS21002_CTRL_REG0_SPIW_MASK ((uint8_t) 0x20)
444#define FXAS21002_CTRL_REG0_SPIW_SHIFT ((uint8_t) 5)
445
446#define FXAS21002_CTRL_REG0_BW_MASK ((uint8_t) 0xC0)
447#define FXAS21002_CTRL_REG0_BW_SHIFT ((uint8_t) 6)
448
449
450/*
451** CTRL_REG0 - Bit field value definitions
452*/
453#define FXAS21002_CTRL_REG0_FS_DPS2000 ((uint8_t) 0x00) /* 2000 degrees per second (4000 dps if CTRL_REG3 : */
454 /* FS_DOUBLE = 1). */
455#define FXAS21002_CTRL_REG0_FS_DPS1000 ((uint8_t) 0x01) /* 1000 degrees per second (2000 dps if CTRL_REG3 : */
456 /* FS_DOUBLE = 1). */
457#define FXAS21002_CTRL_REG0_FS_DPS500 ((uint8_t) 0x02) /* 500 degrees per second (1000 dps if CTRL_REG3 : */
458 /* FS_DOUBLE = 1). */
459#define FXAS21002_CTRL_REG0_FS_DPS250 ((uint8_t) 0x03) /* 250 degrees per second (500 dps if CTRL_REG3 : */
460 /* FS_DOUBLE = 1). */
461#define FXAS21002_CTRL_REG0_HPF_EN_ENABLE ((uint8_t) 0x04)
462#define FXAS21002_CTRL_REG0_HPF_EN_DISABLE ((uint8_t) 0x00)
463#define FXAS21002_CTRL_REG0_SPIW_4WIRE ((uint8_t) 0x00) /* SPI 4-wire mode (default). */
464#define FXAS21002_CTRL_REG0_SPIW_3WIRE ((uint8_t) 0x20) /* SPI 3-wire mode (MOSI pin is used for SPI input */
465 /* and output signals). */
466/*------------------------------*/
467
468
469
470/*--------------------------------
471** Register: RT_CFG
472** Enum: FXAS21002_RT_CFG
473** --
474** Offset : 0x0E - Used to enable the Rate Threshold interrupt generation.
475** ------------------------------*/
476typedef union {
477 struct {
478 uint8_t xtefe : 1; /* Event flag enable on X rate. */
479
480 uint8_t ytefe : 1; /* Event flag enable on Y rate. */
481
482 uint8_t ztefe : 1; /* Event flag enable on Z rate. */
483
484 uint8_t ele : 1; /* Event latch enable. */
485
486 } b;
487 uint8_t w;
488} FXAS21002_RT_CFG_t;
489
490
491/*
492** RT_CFG - Bit field mask definitions
493*/
494#define FXAS21002_RT_CFG_XTEFE_MASK ((uint8_t) 0x01)
495#define FXAS21002_RT_CFG_XTEFE_SHIFT ((uint8_t) 0)
496
497#define FXAS21002_RT_CFG_YTEFE_MASK ((uint8_t) 0x02)
498#define FXAS21002_RT_CFG_YTEFE_SHIFT ((uint8_t) 1)
499
500#define FXAS21002_RT_CFG_ZTEFE_MASK ((uint8_t) 0x04)
501#define FXAS21002_RT_CFG_ZTEFE_SHIFT ((uint8_t) 2)
502
503#define FXAS21002_RT_CFG_ELE_MASK ((uint8_t) 0x08)
504#define FXAS21002_RT_CFG_ELE_SHIFT ((uint8_t) 3)
505
506
507/*
508** RT_CFG - Bit field value definitions
509*/
510#define FXAS21002_RT_CFG_XTEFE_ENABLE ((uint8_t) 0x01) /* X event detection enabled. */
511#define FXAS21002_RT_CFG_XTEFE_DISABLE ((uint8_t) 0x00) /* X event detection disabled. */
512#define FXAS21002_RT_CFG_YTEFE_ENABLE ((uint8_t) 0x02) /* Y event detection enabled. */
513#define FXAS21002_RT_CFG_YTEFE_DISABLE ((uint8_t) 0x00) /* Y event detection disabled. */
514#define FXAS21002_RT_CFG_ZTEFE_ENABLE ((uint8_t) 0x04) /* Z event detection enabled. */
515#define FXAS21002_RT_CFG_ZTEFE_DISABLE ((uint8_t) 0x00) /* Z event detection disabled. */
516#define FXAS21002_RT_CFG_ELE_ENABLE ((uint8_t) 0x08) /* Event flag latch enabled. */
517#define FXAS21002_RT_CFG_ELE_DISABLE ((uint8_t) 0x00) /* Event flag latch disabled. */
518/*------------------------------*/
519
520
521
522/*--------------------------------
523** Register: RT_SRC
524** Enum: FXAS21002_RT_SRC
525** --
526** Offset : 0x0F - Indicates the source of the Rate Threshold event. It also clears the RT_SRC flag in the INT_SOURCE_FLAG register.
527** ------------------------------*/
528typedef union {
529 struct {
530 uint8_t x_rt_pol : 1; /* Polarity of X event. */
531
532 uint8_t xrt : 1; /* X rate Event. */
533
534 uint8_t y_rt_pol : 1; /* Polarity of Y event. */
535
536 uint8_t yrt : 1; /* Y rate event. */
537
538 uint8_t z_rt_pol : 1; /* Polarity of Z event. */
539
540 uint8_t zrt : 1; /* Z rate event. */
541
542 uint8_t ea : 1; /* Event active flag. */
543
544 } b;
545 uint8_t w;
546} FXAS21002_RT_SRC_t;
547
548
549/*
550** RT_SRC - Bit field mask definitions
551*/
552#define FXAS21002_RT_SRC_X_RT_POL_MASK ((uint8_t) 0x01)
553#define FXAS21002_RT_SRC_X_RT_POL_SHIFT ((uint8_t) 0)
554
555#define FXAS21002_RT_SRC_XRT_MASK ((uint8_t) 0x02)
556#define FXAS21002_RT_SRC_XRT_SHIFT ((uint8_t) 1)
557
558#define FXAS21002_RT_SRC_Y_RT_POL_MASK ((uint8_t) 0x04)
559#define FXAS21002_RT_SRC_Y_RT_POL_SHIFT ((uint8_t) 2)
560
561#define FXAS21002_RT_SRC_YRT_MASK ((uint8_t) 0x08)
562#define FXAS21002_RT_SRC_YRT_SHIFT ((uint8_t) 3)
563
564#define FXAS21002_RT_SRC_Z_RT_POL_MASK ((uint8_t) 0x10)
565#define FXAS21002_RT_SRC_Z_RT_POL_SHIFT ((uint8_t) 4)
566
567#define FXAS21002_RT_SRC_ZRT_MASK ((uint8_t) 0x20)
568#define FXAS21002_RT_SRC_ZRT_SHIFT ((uint8_t) 5)
569
570#define FXAS21002_RT_SRC_EA_MASK ((uint8_t) 0x40)
571#define FXAS21002_RT_SRC_EA_SHIFT ((uint8_t) 6)
572
573
574/*
575** RT_SRC - Bit field value definitions
576*/
577#define FXAS21002_RT_SRC_X_RT_POL_POS ((uint8_t) 0x00) /* Rate Event was Positive. */
578#define FXAS21002_RT_SRC_X_RT_POL_NEG ((uint8_t) 0x01) /* Rate Event was Negative. */
579#define FXAS21002_RT_SRC_XRT_LOWER ((uint8_t) 0x00) /* Rate lower than RT_THS value. */
580#define FXAS21002_RT_SRC_XRT_GREATER ((uint8_t) 0x02) /* Rate greater than RT_THS value. Event has occured. */
581#define FXAS21002_RT_SRC_Y_RT_POL_POS ((uint8_t) 0x00) /* Rate Event was Positive. */
582#define FXAS21002_RT_SRC_Y_RT_POL_NEG ((uint8_t) 0x04) /* Rate Event was Negative. */
583#define FXAS21002_RT_SRC_YRT_LOWER ((uint8_t) 0x00) /* Rate lower than RT_THS value. */
584#define FXAS21002_RT_SRC_YRT_GREATER ((uint8_t) 0x08) /* Rate greater than RT_THS value. Event has occured. */
585#define FXAS21002_RT_SRC_Z_RT_POL_POS ((uint8_t) 0x00) /* Rate Event was Positive. */
586#define FXAS21002_RT_SRC_Z_RT_POL_NEG ((uint8_t) 0x10) /* Rate Event was Negative. */
587#define FXAS21002_RT_SRC_ZRT_LOWER ((uint8_t) 0x00) /* Rate lower than RT_THS value. */
588#define FXAS21002_RT_SRC_ZRT_GREATER ((uint8_t) 0x20) /* Rate greater than RT_THS value. Event has occured. */
589#define FXAS21002_RT_SRC_EA_NOEVENT ((uint8_t) 0x00) /* No event flags have been asserted. */
590#define FXAS21002_RT_SRC_EA_EVENT ((uint8_t) 0x40) /* One or more event flags have been asserted. */
591/*------------------------------*/
592
593
594
595/*--------------------------------
596** Register: RT_THS
597** Enum: FXAS21002_RT_THS
598** --
599** Offset : 0x10 - The RT_THS register sets the threshold limit for the detection of the rate and the debounce counter mode.
600** ------------------------------*/
601typedef union {
602 struct {
603 uint8_t ths : 7; /* Unsigned 7-bit rate threshold value; The contents should only be modified */
604 /* when the device is in Standby mode; The internal state of the Rate */
605 /* Threshold function is reset when a transition from Standby to Active or */
606 /* Ready to Active modes occurs. */
607
608 uint8_t dbcntm : 1; /* Debounce counter mode selection. */
609
610 } b;
611 uint8_t w;
612} FXAS21002_RT_THS_t;
613
614
615/*
616** RT_THS - Bit field mask definitions
617*/
618#define FXAS21002_RT_THS_THS_MASK ((uint8_t) 0x7F)
619#define FXAS21002_RT_THS_THS_SHIFT ((uint8_t) 0)
620
621#define FXAS21002_RT_THS_DBCNTM_MASK ((uint8_t) 0x80)
622#define FXAS21002_RT_THS_DBCNTM_SHIFT ((uint8_t) 7)
623
624
625/*
626** RT_THS - Bit field value definitions
627*/
628#define FXAS21002_RT_THS_DBCNTM_CLEAR ((uint8_t) 0x80) /* Clear counter when angular rate is below the */
629 /* threshold value. */
630#define FXAS21002_RT_THS_DBCNTM_DECREMENT ((uint8_t) 0x00) /* Decrement counter on every ODR cycle that the */
631 /* angular rate is below the threshold value. */
632/*------------------------------*/
633
634
635
636/*--------------------------------
637** Register: RT_COUNT
638** Enum: FXAS21002_RT_COUNT
639** --
640** Offset : 0x11 - Sets the number of debounce counts.
641** ------------------------------*/
642typedef uint8_t FXAS21002_RT_COUNT_t;
643
644
645
646/*--------------------------------
647** Register: TEMP
648** Enum: FXAS21002_TEMP
649** --
650** Offset : 0x12 - The TEMP register contains an 8-bit 2's complement temperature value with a range of �128 �C to +127 �C and a scaling of 1 �C/LSB.
651** ------------------------------*/
652typedef uint8_t FXAS21002_TEMP_t;
653
654
655
656/*--------------------------------
657** Register: CTRL_REG1
658** Enum: FXAS21002_CTRL_REG1
659** --
660** Offset : 0x13 - The CTRL_REG1 register is used to configure the device ODR, set the operating mode, soft-reset the device, and exercise the Self-Test function.
661** ------------------------------*/
662typedef union {
663 struct {
664 uint8_t mode : 2; /* Operational Mode. */
665
666 uint8_t dr : 3; /* Output Data Rate selection. */
667
668 uint8_t st : 1; /* Self-Test Enable. */
669
670 uint8_t rst : 1; /* Software Reset. */
671
672 } b;
673 uint8_t w;
674} FXAS21002_CTRL_REG1_t;
675
676
677/*
678** CTRL_REG1 - Bit field mask definitions
679*/
680#define FXAS21002_CTRL_REG1_MODE_MASK ((uint8_t) 0x03)
681#define FXAS21002_CTRL_REG1_MODE_SHIFT ((uint8_t) 0)
682
683#define FXAS21002_CTRL_REG1_DR_MASK ((uint8_t) 0x1C)
684#define FXAS21002_CTRL_REG1_DR_SHIFT ((uint8_t) 2)
685
686#define FXAS21002_CTRL_REG1_ST_MASK ((uint8_t) 0x20)
687#define FXAS21002_CTRL_REG1_ST_SHIFT ((uint8_t) 5)
688
689#define FXAS21002_CTRL_REG1_RST_MASK ((uint8_t) 0x40)
690#define FXAS21002_CTRL_REG1_RST_SHIFT ((uint8_t) 6)
691
692
693/*
694** CTRL_REG1 - Bit field value definitions
695*/
696#define FXAS21002_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* Standby Mode. Register setting allowed. Lowest */
697 /* power. */
698#define FXAS21002_CTRL_REG1_MODE_READY ((uint8_t) 0x01) /* Ready Mode. The device is ready to measure */
699 /* angular rate but no data acquisitions are being */
700 /* made. Register reads only. Reduced power. */
701#define FXAS21002_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x02) /* Active Mode. The device is fully functional. */
702 /* Register reads only. Maximum power. */
703#define FXAS21002_CTRL_REG1_DR_800HZ ((uint8_t) 0x00)
704#define FXAS21002_CTRL_REG1_DR_400HZ ((uint8_t) 0x04)
705#define FXAS21002_CTRL_REG1_DR_200HZ ((uint8_t) 0x08)
706#define FXAS21002_CTRL_REG1_DR_100HZ ((uint8_t) 0x0c)
707#define FXAS21002_CTRL_REG1_DR_50HZ ((uint8_t) 0x10)
708#define FXAS21002_CTRL_REG1_DR_25HZ ((uint8_t) 0x14)
709#define FXAS21002_CTRL_REG1_DR_12_5HZ ((uint8_t) 0x18)
710#define FXAS21002_CTRL_REG1_ST_ENABLE ((uint8_t) 0x20)
711#define FXAS21002_CTRL_REG1_ST_DISABLE ((uint8_t) 0x00)
712#define FXAS21002_CTRL_REG1_RST_TRIGGER ((uint8_t) 0x40)
713#define FXAS21002_CTRL_REG1_RST_NOTTRIGGERED ((uint8_t) 0x00)
714/*------------------------------*/
715
716
717
718/*--------------------------------
719** Register: CTRL_REG2
720** Enum: FXAS21002_CTRL_REG2
721** --
722** Offset : 0x14 - This register enables and assigns the output pin(s) and logic polarities for the various interrupt sources available on the device.
723** ------------------------------*/
724typedef union {
725 struct {
726 uint8_t pp_od : 1; /* INT1 and INT2 pin output driver configuration. */
727
728 uint8_t ipol : 1; /* Interrupt logic polarity. */
729
730 uint8_t int_en_drdy : 1; /* Data ready interrupt enable. */
731
732 uint8_t int_cfg_drdy : 1; /* Data-ready interrupt pin routing. */
733
734 uint8_t int_en_rt : 1; /* Rate threshold interrupt enable. */
735
736 uint8_t int_cfg_rt : 1; /* Rate threshold interrupt pin routing. */
737
738 uint8_t int_en_fifo : 1; /* FIFO Interrupt Enable. */
739
740 uint8_t int_cfg_fifo : 1; /* FIFO interrupt pin routing. */
741
742 } b;
743 uint8_t w;
744} FXAS21002_CTRL_REG2_t;
745
746
747/*
748** CTRL_REG2 - Bit field mask definitions
749*/
750#define FXAS21002_CTRL_REG2_PP_OD_MASK ((uint8_t) 0x01)
751#define FXAS21002_CTRL_REG2_PP_OD_SHIFT ((uint8_t) 0)
752
753#define FXAS21002_CTRL_REG2_IPOL_MASK ((uint8_t) 0x02)
754#define FXAS21002_CTRL_REG2_IPOL_SHIFT ((uint8_t) 1)
755
756#define FXAS21002_CTRL_REG2_INT_EN_DRDY_MASK ((uint8_t) 0x04)
757#define FXAS21002_CTRL_REG2_INT_EN_DRDY_SHIFT ((uint8_t) 2)
758
759#define FXAS21002_CTRL_REG2_INT_CFG_DRDY_MASK ((uint8_t) 0x08)
760#define FXAS21002_CTRL_REG2_INT_CFG_DRDY_SHIFT ((uint8_t) 3)
761
762#define FXAS21002_CTRL_REG2_INT_EN_RT_MASK ((uint8_t) 0x10)
763#define FXAS21002_CTRL_REG2_INT_EN_RT_SHIFT ((uint8_t) 4)
764
765#define FXAS21002_CTRL_REG2_INT_CFG_RT_MASK ((uint8_t) 0x20)
766#define FXAS21002_CTRL_REG2_INT_CFG_RT_SHIFT ((uint8_t) 5)
767
768#define FXAS21002_CTRL_REG2_INT_EN_FIFO_MASK ((uint8_t) 0x40)
769#define FXAS21002_CTRL_REG2_INT_EN_FIFO_SHIFT ((uint8_t) 6)
770
771#define FXAS21002_CTRL_REG2_INT_CFG_FIFO_MASK ((uint8_t) 0x80)
772#define FXAS21002_CTRL_REG2_INT_CFG_FIFO_SHIFT ((uint8_t) 7)
773
774
775/*
776** CTRL_REG2 - Bit field value definitions
777*/
778#define FXAS21002_CTRL_REG2_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-pull output driver. */
779#define FXAS21002_CTRL_REG2_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open-drain output driver. */
780#define FXAS21002_CTRL_REG2_IPOL_ACTIVE_LOW ((uint8_t) 0x00)
781#define FXAS21002_CTRL_REG2_IPOL_ACTIVE_HIGH ((uint8_t) 0x02)
782#define FXAS21002_CTRL_REG2_INT_EN_DRDY_ENABLE ((uint8_t) 0x04)
783#define FXAS21002_CTRL_REG2_INT_EN_DRDY_DISABLE ((uint8_t) 0x00)
784#define FXAS21002_CTRL_REG2_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
785#define FXAS21002_CTRL_REG2_INT_CFG_DRDY_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */
786#define FXAS21002_CTRL_REG2_INT_EN_RT_ENABLE ((uint8_t) 0x10)
787#define FXAS21002_CTRL_REG2_INT_EN_RT_DISABLE ((uint8_t) 0x00)
788#define FXAS21002_CTRL_REG2_INT_CFG_RT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
789#define FXAS21002_CTRL_REG2_INT_CFG_RT_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */
790#define FXAS21002_CTRL_REG2_INT_EN_FIFO_ENABLE ((uint8_t) 0x40)
791#define FXAS21002_CTRL_REG2_INT_EN_FIFO_DISABLE ((uint8_t) 0x00)
792#define FXAS21002_CTRL_REG2_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
793#define FXAS21002_CTRL_REG2_INT_CFG_FIFO_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */
794/*------------------------------*/
795
796
797
798/*--------------------------------
799** Register: CTRL_REG3
800** Enum: FXAS21002_CTRL_REG3
801** --
802** Offset : 0x15 - Auto-increment address configuration, external power control, Full Scale Range (FSR) expansion
803** ------------------------------*/
804typedef union {
805 struct {
806 uint8_t fs_double : 1; /* Increases the dynamic range for each CTRL_REG0 : FS selection by a factor */
807 /* of two. */
808
809 uint8_t _reserved_ : 1;
810 uint8_t extctrlen : 1; /* External power mode control input. */
811
812 uint8_t wraptoone : 1; /* Auto-increment read address pointer roll-over behavior. */
813
814 } b;
815 uint8_t w;
816} FXAS21002_CTRL_REG3_t;
817
818
819/*
820** CTRL_REG3 - Bit field mask definitions
821*/
822#define FXAS21002_CTRL_REG3_FS_DOUBLE_MASK ((uint8_t) 0x01)
823#define FXAS21002_CTRL_REG3_FS_DOUBLE_SHIFT ((uint8_t) 0)
824
825#define FXAS21002_CTRL_REG3_EXTCTRLEN_MASK ((uint8_t) 0x04)
826#define FXAS21002_CTRL_REG3_EXTCTRLEN_SHIFT ((uint8_t) 2)
827
828#define FXAS21002_CTRL_REG3_WRAPTOONE_MASK ((uint8_t) 0x08)
829#define FXAS21002_CTRL_REG3_WRAPTOONE_SHIFT ((uint8_t) 3)
830
831
832/*
833** CTRL_REG3 - Bit field value definitions
834*/
835#define FXAS21002_CTRL_REG3_FS_DOUBLE_ENABLE ((uint8_t) 0x01) /* Maximum full-scale range selections are doubled */
836 /* (4000, 2000, 1000, 500 dps). */
837#define FXAS21002_CTRL_REG3_FS_DOUBLE_DISABLE ((uint8_t) 0x00) /* Maximum full-scale range selections are as per */
838 /* selectable full-scale ranges (2000, 1000, 500, */
839 /* 250 dps). */
840#define FXAS21002_CTRL_REG3_EXTCTRLEN_INT2 ((uint8_t) 0x00) /* INT2 pin is used as an interrupt output */
841 /* (default). */
842#define FXAS21002_CTRL_REG3_EXTCTRLEN_POWER_CONTROL ((uint8_t) 0x04) /* INT2 pin becomes an input pin that may be used */
843 /* to control the power mode. */
844#define FXAS21002_CTRL_REG3_WRAPTOONE_ROLL_STATUS ((uint8_t) 0x00) /* The auto-increment read address pointer rolls */
845 /* over to address 0x00 (STATUS) after the Z-axis */
846 /* LSB is read (default). */
847#define FXAS21002_CTRL_REG3_WRAPTOONE_ROLL_DATA ((uint8_t) 0x08) /* The auto-increment pointer rolls over to address */
848 /* 0x01 (X-axis MSB) in order to facilitate the */
849 /* faster read out of the FIFO data in a single */
850 /* burst read operation. */
851/*------------------------------*/
852
853
854#ifdef __cplusplus
855}
856#endif
857
858#endif /* DRIVER_FXAS21002_H_ */
FXAS21002_CTRL_REG0_t
Definition driver_fxas21002.h:411
FXAS21002_CTRL_REG1_t
Definition driver_fxas21002.h:662
FXAS21002_CTRL_REG2_t
Definition driver_fxas21002.h:724
FXAS21002_CTRL_REG3_t
Definition driver_fxas21002.h:804
FXAS21002_DR_STATUS_t
Definition driver_fxas21002.h:124
FXAS21002_F_EVENT_t
Definition driver_fxas21002.h:292
FXAS21002_F_SETUP_t
Definition driver_fxas21002.h:255
FXAS21002_F_STATUS_t
Definition driver_fxas21002.h:211
FXAS21002_INT_SRC_FLAG_t
Definition driver_fxas21002.h:328
FXAS21002_RT_CFG_t
Definition driver_fxas21002.h:476
FXAS21002_RT_SRC_t
Definition driver_fxas21002.h:528
FXAS21002_RT_THS_t
Definition driver_fxas21002.h:601
FXAS21002_WHO_AM_I_t
Definition driver_fxas21002.h:379
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