Sensor Fusion Library 0.6.1
Orientation sensing for Espressif (ESP32, ESP8266) processors
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driver_fxos8700_registers.h
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1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
14#ifndef DRIVER_FXOS8700_REGISTERS_H_
15#define DRIVER_FXOS8700_REGISTERS_H_
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
24enum {
25 FXOS8700_STATUS = 0x00,
26 FXOS8700_OUT_X_MSB = 0x01,
27 FXOS8700_OUT_X_LSB = 0x02,
28 FXOS8700_OUT_Y_MSB = 0x03,
29 FXOS8700_OUT_Y_LSB = 0x04,
30 FXOS8700_OUT_Z_MSB = 0x05,
31 FXOS8700_OUT_Z_LSB = 0x06,
32 FXOS8700_F_SETUP = 0x09,
33 FXOS8700_TRIG_CFG = 0x0A,
34 FXOS8700_SYSMOD = 0x0B,
35 FXOS8700_INT_SOURCE = 0x0C,
36 FXOS8700_WHO_AM_I = 0x0D,
37 FXOS8700_XYZ_DATA_CFG = 0x0E,
38 FXOS8700_HP_FILTER_CUTOFF = 0x0F,
39 FXOS8700_PL_STATUS = 0x10,
40 FXOS8700_PL_CFG = 0x11,
41 FXOS8700_PL_COUNT = 0x12,
42 FXOS8700_PL_BF_ZCOMP = 0x13,
43 FXOS8700_PL_THS_REG = 0x14,
44 FXOS8700_A_FFMT_CFG = 0x15,
45 FXOS8700_A_FFMT_SRC = 0x16,
46 FXOS8700_A_FFMT_THS = 0x17,
47 FXOS8700_A_FFMT_COUNT = 0x18,
48 FXOS8700_TRANSIENT_CFG = 0x1D,
49 FXOS8700_TRANSIENT_SRC = 0x1E,
50 FXOS8700_TRANSIENT_THS = 0x1F,
51 FXOS8700_TRANSIENT_COUNT = 0x20,
52 FXOS8700_PULSE_CFG = 0x21,
53 FXOS8700_PULSE_SRC = 0x22,
54 FXOS8700_PULSE_THSX = 0x23,
55 FXOS8700_PULSE_THSY = 0x24,
56 FXOS8700_PULSE_THSZ = 0x25,
57 FXOS8700_PULSE_TMLT = 0x26,
58 FXOS8700_PULSE_LTCY = 0x27,
59 FXOS8700_PULSE_WIND = 0x28,
60 FXOS8700_ASLP_COUNT = 0x29,
61 FXOS8700_CTRL_REG1 = 0x2A,
62 FXOS8700_CTRL_REG2 = 0x2B,
63 FXOS8700_CTRL_REG3 = 0x2C,
64 FXOS8700_CTRL_REG4 = 0x2D,
65 FXOS8700_CTRL_REG5 = 0x2E,
66 FXOS8700_OFF_X = 0x2F,
67 FXOS8700_OFF_Y = 0x30,
68 FXOS8700_OFF_Z = 0x31,
69 FXOS8700_M_DR_STATUS = 0x32,
70 FXOS8700_M_OUT_X_MSB = 0x33,
71 FXOS8700_M_OUT_X_LSB = 0x34,
72 FXOS8700_M_OUT_Y_MSB = 0x35,
73 FXOS8700_M_OUT_Y_LSB = 0x36,
74 FXOS8700_M_OUT_Z_MSB = 0x37,
75 FXOS8700_M_OUT_Z_LSB = 0x38,
76 FXOS8700_CMP_X_MSB = 0x39,
77 FXOS8700_CMP_X_LSB = 0x3A,
78 FXOS8700_CMP_Y_MSB = 0x3B,
79 FXOS8700_CMP_Y_LSB = 0x3C,
80 FXOS8700_CMP_Z_MSB = 0x3D,
81 FXOS8700_CMP_Z_LSB = 0x3E,
82 FXOS8700_M_OFF_X_MSB = 0x3F,
83 FXOS8700_M_OFF_X_LSB = 0x40,
84 FXOS8700_M_OFF_Y_MSB = 0x41,
85 FXOS8700_M_OFF_Y_LSB = 0x42,
86 FXOS8700_M_OFF_Z_MSB = 0x43,
87 FXOS8700_M_OFF_Z_LSB = 0x44,
88 FXOS8700_MAX_X_MSB = 0x45,
89 FXOS8700_MAX_X_LSB = 0x46,
90 FXOS8700_MAX_Y_MSB = 0x47,
91 FXOS8700_MAX_Y_LSB = 0x48,
92 FXOS8700_MAX_Z_MSB = 0x49,
93 FXOS8700_MAX_Z_LSB = 0x4A,
94 FXOS8700_MIN_X_MSB = 0x4B,
95 FXOS8700_MIN_X_LSB = 0x4C,
96 FXOS8700_MIN_Y_MSB = 0x4D,
97 FXOS8700_MIN_Y_LSB = 0x4E,
98 FXOS8700_MIN_Z_MSB = 0x4F,
99 FXOS8700_MIN_Z_LSB = 0x50,
100 FXOS8700_TEMP = 0x51,
101 FXOS8700_M_THS_CFG = 0x52,
102 FXOS8700_M_THS_SRC = 0x53,
103 FXOS8700_M_THS_X_MSB = 0x54,
104 FXOS8700_M_THS_X_LSB = 0x55,
105 FXOS8700_M_THS_Y_MSB = 0x56,
106 FXOS8700_M_THS_Y_LSB = 0x57,
107 FXOS8700_M_THS_Z_MSB = 0x58,
108 FXOS8700_M_THS_Z_LSB = 0x59,
109 FXOS8700_M_THS_COUNT = 0x5A,
110 FXOS8700_M_CTRL_REG1 = 0x5B,
111 FXOS8700_M_CTRL_REG2 = 0x5C,
112 FXOS8700_M_CTRL_REG3 = 0x5D,
113 FXOS8700_M_INT_SRC = 0x5E,
114 FXOS8700_A_VECM_CFG = 0x5F,
115 FXOS8700_A_VECM_THS_MSB = 0x60,
116 FXOS8700_A_VECM_THS_LSB = 0x61,
117 FXOS8700_A_VECM_CNT = 0x62,
118 FXOS8700_A_VECM_INITX_MSB = 0x63,
119 FXOS8700_A_VECM_INITX_LSB = 0x64,
120 FXOS8700_A_VECM_INITY_MSB = 0x65,
121 FXOS8700_A_VECM_INITY_LSB = 0x66,
122 FXOS8700_A_VECM_INITZ_MSB = 0x67,
123 FXOS8700_A_VECM_INITZ_LSB = 0x68,
124 FXOS8700_M_VECM_CFG = 0x69,
125 FXOS8700_M_VECM_THS_MSB = 0x6A,
126 FXOS8700_M_VECM_THS_LSB = 0x6B,
127 FXOS8700_M_VECM_CNT = 0x6C,
128 FXOS8700_M_VECM_INITX_MSB = 0x6D,
129 FXOS8700_M_VECM_INITX_LSB = 0x6E,
130 FXOS8700_M_VECM_INITY_MSB = 0x6F,
131 FXOS8700_M_VECM_INITY_LSB = 0x70,
132 FXOS8700_M_VECM_INITZ_MSB = 0x71,
133 FXOS8700_M_VECM_INITZ_LSB = 0x72,
134 FXOS8700_A_FFMT_THS_X_MSB = 0x73,
135 FXOS8700_A_FFMT_THS_X_LSB = 0x74,
136 FXOS8700_A_FFMT_THS_Y_MSB = 0x75,
137 FXOS8700_A_FFMT_THS_Y_LSB = 0x76,
138 FXOS8700_A_FFMT_THS_Z_MSB = 0x77,
139 FXOS8700_A_FFMT_THS_Z_LSB = 0x78,
140};
141
142#define FXOS8700_DEVICE_ADDR_SA_00 (0x1E)
143
144#define FXOS8700_DEVICE_ADDR_SA_01 (0x1D)
145
146#define FXOS8700_DEVICE_ADDR_SA_10 (0x1C)
147
148#define FXOS8700_DEVICE_ADDR_SA_11 (0x1F)
149
150
151#define FXOS8700_WHO_AM_I_PROD_VALUE (0xC7)
152
153
158/*--------------------------------
159** Register: DR_STATUS
160** Enum: FXOS8700_DR_STATUS
161** --
162** Offset : 0x00 - Alias for ::FXOS8700_DR_STATUS or ::FXOS8700_F_STATUS.
163** ------------------------------*/
164typedef union {
165 struct {
166 uint8_t xdr : 1;
167 uint8_t ydr : 1;
168 uint8_t zdr : 1;
169 uint8_t zyxdr : 1;
170 uint8_t xow : 1;
171 uint8_t yow : 1;
172 uint8_t zow : 1;
173 uint8_t zyxow : 1;
174 } b;
175 uint8_t w;
176} FXOS8700_DR_STATUS_t;
177
178
179/*
180** DR_STATUS - Bit field mask definitions
181*/
182#define FXOS8700_DR_STATUS_XDR_MASK ((uint8_t) 0x01)
183#define FXOS8700_DR_STATUS_XDR_SHIFT ((uint8_t) 0)
184
185#define FXOS8700_DR_STATUS_YDR_MASK ((uint8_t) 0x02)
186#define FXOS8700_DR_STATUS_YDR_SHIFT ((uint8_t) 1)
187
188#define FXOS8700_DR_STATUS_ZDR_MASK ((uint8_t) 0x04)
189#define FXOS8700_DR_STATUS_ZDR_SHIFT ((uint8_t) 2)
190
191#define FXOS8700_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
192#define FXOS8700_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
193
194#define FXOS8700_DR_STATUS_XOW_MASK ((uint8_t) 0x10)
195#define FXOS8700_DR_STATUS_XOW_SHIFT ((uint8_t) 4)
196
197#define FXOS8700_DR_STATUS_YOW_MASK ((uint8_t) 0x20)
198#define FXOS8700_DR_STATUS_YOW_SHIFT ((uint8_t) 5)
199
200#define FXOS8700_DR_STATUS_ZOW_MASK ((uint8_t) 0x40)
201#define FXOS8700_DR_STATUS_ZOW_SHIFT ((uint8_t) 6)
202
203#define FXOS8700_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
204#define FXOS8700_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
205
206
207/*
208** DR_STATUS - Bit field value definitions
209*/
210#define FXOS8700_DR_STATUS_XDR_DRDY ((uint8_t) 0x01) /* xdr is set to 1 whenever a new X-axis data */
211 /* acquisition is completed. xdr is cleared anytime */
212 /* the OUT_X_MSB register is read. */
213#define FXOS8700_DR_STATUS_YDR_DRDY ((uint8_t) 0x02) /* ydr is set to 1 whenever a new Y-axis data */
214 /* acquisition is completed. xdr is cleared anytime */
215 /* the OUT_Y_MSB register is read. */
216#define FXOS8700_DR_STATUS_ZDR_DRDY ((uint8_t) 0x04) /* zdr is set to 1 whenever a new Z-axis data */
217 /* acquisition is completed. xdr is cleared anytime */
218 /* the OUT_Z_MSB register is read. */
219#define FXOS8700_DR_STATUS_ZYXDR_DRDY ((uint8_t) 0x08) /* zyxdr signals that a new acquisition for any of */
220 /* the enabled channels is available. zyxdr is */
221 /* cleared when the high-bytes of the acceleration */
222 /* data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) are read. */
223#define FXOS8700_DR_STATUS_XOW_OWR ((uint8_t) 0x10)
224#define FXOS8700_DR_STATUS_YOW_OWR ((uint8_t) 0x20)
225#define FXOS8700_DR_STATUS_ZOW_OWR ((uint8_t) 0x40)
226#define FXOS8700_DR_STATUS_ZYXOW_OWR ((uint8_t) 0x80)
227/*------------------------------*/
228
229
230
231/*--------------------------------
232** Register: F_STATUS
233** Enum: FXOS8700_F_STATUS
234** --
235** Offset : 0x00 - Fifo Status register
236** ------------------------------*/
237typedef union {
238 struct {
239 uint8_t f_cnt : 6; /* These bits indicate the number of acceleration samples currently stored in */
240 /* the FIFO buffer. Count 0b00_0000 indicates that the FIFO is empty */
241
242 uint8_t f_wmrk_flag : 1;
243 uint8_t f_ovf : 1;
244 } b;
245 uint8_t w;
246} FXOS8700_F_STATUS_t;
247
248
249/*
250** F_STATUS - Bit field mask definitions
251*/
252#define FXOS8700_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
253#define FXOS8700_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
254
255#define FXOS8700_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40)
256#define FXOS8700_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6)
257
258#define FXOS8700_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
259#define FXOS8700_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
260
261
262/*
263** F_STATUS - Bit field value definitions
264*/
265#define FXOS8700_F_STATUS_F_WMRK_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected */
266#define FXOS8700_F_STATUS_F_WMRK_FLAG_EVTDET ((uint8_t) 0x40)
267#define FXOS8700_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected */
268#define FXOS8700_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO overflow event detected */
269/*------------------------------*/
270
271
272
273/*--------------------------------
274** Register: OUT_X_MSB
275** Enum: FXOS8700_OUT_X_MSB
276** --
277** Offset : 0x01 - MSB of Accelerometer X value
278** ------------------------------*/
279typedef union {
280 struct {
281 uint8_t xd; /* - 14-bit X-axis measurement data bits 13:6. */
282
283 } b;
284 uint8_t w;
285} FXOS8700_OUT_X_MSB_t;
286
287
288/*
289** OUT_X_MSB - Bit field mask definitions
290*/
291#define FXOS8700_OUT_X_MSB_XD_MASK ((uint8_t) 0xFF)
292#define FXOS8700_OUT_X_MSB_XD_SHIFT ((uint8_t) 0)
293
294
295/*------------------------------*/
296
297
298
299/*--------------------------------
300** Register: OUT_X_LSB
301** Enum: FXOS8700_OUT_X_LSB
302** --
303** Offset : 0x02 - LSB of Accelerometer X value
304** ------------------------------*/
305typedef union {
306 struct {
307 uint8_t _reserved_ : 2;
308 uint8_t xd : 6; /* - 14-bit X-axis measurement data bits 5:0. */
309
310 } b;
311 uint8_t w;
312} FXOS8700_OUT_X_LSB_t;
313
314
315/*
316** OUT_X_LSB - Bit field mask definitions
317*/
318#define FXOS8700_OUT_X_LSB_XD_MASK ((uint8_t) 0xFC)
319#define FXOS8700_OUT_X_LSB_XD_SHIFT ((uint8_t) 2)
320
321
322/*------------------------------*/
323
324
325
326/*--------------------------------
327** Register: OUT_Y_MSB
328** Enum: FXOS8700_OUT_Y_MSB
329** --
330** Offset : 0x03 - 14-bit Y-axis measurement data bits 13:6.
331** ------------------------------*/
332typedef union {
333 struct {
334 uint8_t yd; /* - 14-bit Y-axis measurement data bits 13:6. */
335
336 } b;
337 uint8_t w;
338} FXOS8700_OUT_Y_MSB_t;
339
340
341/*
342** OUT_Y_MSB - Bit field mask definitions
343*/
344#define FXOS8700_OUT_Y_MSB_YD_MASK ((uint8_t) 0xFF)
345#define FXOS8700_OUT_Y_MSB_YD_SHIFT ((uint8_t) 0)
346
347
348/*------------------------------*/
349
350
351
352/*--------------------------------
353** Register: OUT_Y_LSB
354** Enum: FXOS8700_OUT_Y_LSB
355** --
356** Offset : 0x04 - 14-bit Y-axis measurement data bits 5:0.
357** ------------------------------*/
358typedef union {
359 struct {
360 uint8_t _reserved_ : 2;
361 uint8_t yd : 6; /* - 14-bit Y-axis measurement data bits 5:0. */
362
363 } b;
364 uint8_t w;
365} FXOS8700_OUT_Y_LSB_t;
366
367
368/*
369** OUT_Y_LSB - Bit field mask definitions
370*/
371#define FXOS8700_OUT_Y_LSB_YD_MASK ((uint8_t) 0xFC)
372#define FXOS8700_OUT_Y_LSB_YD_SHIFT ((uint8_t) 2)
373
374
375/*------------------------------*/
376
377
378
379/*--------------------------------
380** Register: OUT_Z_MSB
381** Enum: FXOS8700_OUT_Z_MSB
382** --
383** Offset : 0x05 - 14-bit Z-axis measurement data bits 13:6.
384** ------------------------------*/
385typedef union {
386 struct {
387 uint8_t zd; /* - 14-bit Z-axis measurement data bits 13:6. */
388
389 } b;
390 uint8_t w;
391} FXOS8700_OUT_Z_MSB_t;
392
393
394/*
395** OUT_Z_MSB - Bit field mask definitions
396*/
397#define FXOS8700_OUT_Z_MSB_ZD_MASK ((uint8_t) 0xFF)
398#define FXOS8700_OUT_Z_MSB_ZD_SHIFT ((uint8_t) 0)
399
400
401/*------------------------------*/
402
403
404
405/*--------------------------------
406** Register: OUT_Z_LSB
407** Enum: FXOS8700_OUT_Z_LSB
408** --
409** Offset : 0x06 - 14-bit Z-axis measurement data bits 5:0.
410** ------------------------------*/
411typedef union {
412 struct {
413 uint8_t _reserved_ : 2;
414 uint8_t zd : 6; /* - 14-bit Z-axis measurement data bits 5:0. */
415
416 } b;
417 uint8_t w;
418} FXOS8700_OUT_Z_LSB_t;
419
420
421/*
422** OUT_Z_LSB - Bit field mask definitions
423*/
424#define FXOS8700_OUT_Z_LSB_ZD_MASK ((uint8_t) 0xFC)
425#define FXOS8700_OUT_Z_LSB_ZD_SHIFT ((uint8_t) 2)
426
427
428/*------------------------------*/
429
430
431
432/*--------------------------------
433** Register: F_SETUP
434** Enum: FXOS8700_F_SETUP
435** --
436** Offset : 0x09 - FIFO setup.
437** ------------------------------*/
438typedef union {
439 struct {
440 uint8_t f_wmrk : 6; /* FIFO sample count watermark */
441
442 uint8_t f_mode : 2; /* - FIFO Buffer operating mode */
443
444 } b;
445 uint8_t w;
446} FXOS8700_F_SETUP_t;
447
448
449/*
450** F_SETUP - Bit field mask definitions
451*/
452#define FXOS8700_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
453#define FXOS8700_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
454
455#define FXOS8700_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
456#define FXOS8700_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
457
458
459/*
460** F_SETUP - Bit field value definitions
461*/
462#define FXOS8700_F_SETUP_F_MODE_FIFO_DISABLE ((uint8_t) 0x00) /* FIFO is disabled */
463#define FXOS8700_F_SETUP_F_MODE_FIFO_CIRC ((uint8_t) 0x40) /* FIFO contains the most recent samples when */
464 /* overflowed (circular buffer). Oldest sample is */
465 /* discarded to be replaced by new sample */
466#define FXOS8700_F_SETUP_F_MODE_FIFO_STOP_OVF ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed */
467#define FXOS8700_F_SETUP_F_MODE_FIFO_TRIGGER ((uint8_t) 0xc0) /* FIFO trigger mode */
468/*------------------------------*/
469
470
471
472/*--------------------------------
473** Register: TRIG_CFG
474** Enum: FXOS8700_TRIG_CFG
475** --
476** Offset : 0x0A - FIFO event trigger configuration register.
477** ------------------------------*/
478typedef union {
479 struct {
480 uint8_t _reserved_ : 1;
481 uint8_t trig_a_vecm : 1;
482 uint8_t trig_a_ffmt : 1;
483 uint8_t trig_pulse : 1;
484 uint8_t trig_lndprt : 1;
485 uint8_t trig_trans : 1;
486 } b;
487 uint8_t w;
488} FXOS8700_TRIG_CFG_t;
489
490
491/*
492** TRIG_CFG - Bit field mask definitions
493*/
494#define FXOS8700_TRIG_CFG_TRIG_A_VECM_MASK ((uint8_t) 0x02)
495#define FXOS8700_TRIG_CFG_TRIG_A_VECM_SHIFT ((uint8_t) 1)
496
497#define FXOS8700_TRIG_CFG_TRIG_A_FFMT_MASK ((uint8_t) 0x04)
498#define FXOS8700_TRIG_CFG_TRIG_A_FFMT_SHIFT ((uint8_t) 2)
499
500#define FXOS8700_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08)
501#define FXOS8700_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3)
502
503#define FXOS8700_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10)
504#define FXOS8700_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4)
505
506#define FXOS8700_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20)
507#define FXOS8700_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5)
508
509
510/*
511** TRIG_CFG - Bit field value definitions
512*/
513#define FXOS8700_TRIG_CFG_TRIG_A_VECM_EN ((uint8_t) 0x02) /* Acceleration vector-magnitude FIFO trigger enable */
514#define FXOS8700_TRIG_CFG_TRIG_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude FIFO trigger disable */
515#define FXOS8700_TRIG_CFG_TRIG_A_FFMT_EN ((uint8_t) 0x04) /* Freefall/motion interrupt FIFO trigger enable */
516#define FXOS8700_TRIG_CFG_TRIG_A_FFMT_DIS ((uint8_t) 0x00) /* Freefall/motion interrupt FIFO trigger disable */
517#define FXOS8700_TRIG_CFG_TRIG_PULSE_EN ((uint8_t) 0x08) /* Pluse interrupt FIFO trigger enable */
518#define FXOS8700_TRIG_CFG_TRIG_PULSE_DIS ((uint8_t) 0x00) /* Pluse FIFO trigger enable */
519#define FXOS8700_TRIG_CFG_TRIG_LNDPRT_EN ((uint8_t) 0x10) /* Landscape/portrait orientation interrupt FIFO */
520 /* trigger enable */
521#define FXOS8700_TRIG_CFG_TRIG_LNDPRT_DIS ((uint8_t) 0x00) /* Landscape/portrait orientation interrupt FIFO */
522 /* trigger disable */
523#define FXOS8700_TRIG_CFG_TRIG_TRANS_EN ((uint8_t) 0x20) /* Transient interrupt FIFO trigger enable */
524#define FXOS8700_TRIG_CFG_TRIG_TRANS_DIS ((uint8_t) 0x00) /* Transient interrupt FIFO trigger disable */
525/*------------------------------*/
526
527
528
529/*--------------------------------
530** Register: SYSMOD
531** Enum: FXOS8700_SYSMOD
532** --
533** Offset : 0x0B - Current system mode.
534** ------------------------------*/
535typedef union {
536 struct {
537 uint8_t sysmod : 2;
538 uint8_t fgt : 5;
539 uint8_t fgerr : 1;
540 } b;
541 uint8_t w;
542} FXOS8700_SYSMOD_t;
543
544
545/*
546** SYSMOD - Bit field mask definitions
547*/
548#define FXOS8700_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
549#define FXOS8700_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
550
551#define FXOS8700_SYSMOD_FGT_MASK ((uint8_t) 0x7C)
552#define FXOS8700_SYSMOD_FGT_SHIFT ((uint8_t) 2)
553
554#define FXOS8700_SYSMOD_FGERR_MASK ((uint8_t) 0x80)
555#define FXOS8700_SYSMOD_FGERR_SHIFT ((uint8_t) 7)
556
557
558/*
559** SYSMOD - Bit field value definitions
560*/
561#define FXOS8700_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* Standby mode */
562#define FXOS8700_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* Wake mode */
563#define FXOS8700_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* Sleep mode */
564/*------------------------------*/
565
566
567
568
569/*--------------------------------
570** Register: INT_SOURCE
571** Enum: FXOS8700_INT_SOURCE
572** --
573** Offset : 0x0C - Interrupt status.
574** ------------------------------*/
575typedef union {
576 struct {
577 uint8_t src_drdy : 1;
578 uint8_t src_a_vecm : 1;
579 uint8_t src_ffmt : 1;
580 uint8_t src_pulse : 1;
581 uint8_t src_lndprt : 1;
582 uint8_t src_trans : 1;
583 uint8_t src_fifo : 1;
584 uint8_t src_aslp : 1;
585 } b;
586 uint8_t w;
587} FXOS8700_INT_SOURCE_t;
588
589
590/*
591** INT_SOURCE - Bit field mask definitions
592*/
593#define FXOS8700_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01)
594#define FXOS8700_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0)
595
596#define FXOS8700_INT_SOURCE_SRC_A_VECM_MASK ((uint8_t) 0x02)
597#define FXOS8700_INT_SOURCE_SRC_A_VECM_SHIFT ((uint8_t) 1)
598
599#define FXOS8700_INT_SOURCE_SRC_FFMT_MASK ((uint8_t) 0x04)
600#define FXOS8700_INT_SOURCE_SRC_FFMT_SHIFT ((uint8_t) 2)
601
602#define FXOS8700_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08)
603#define FXOS8700_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3)
604
605#define FXOS8700_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10)
606#define FXOS8700_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4)
607
608#define FXOS8700_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20)
609#define FXOS8700_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5)
610
611#define FXOS8700_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
612#define FXOS8700_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
613
614#define FXOS8700_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80)
615#define FXOS8700_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7)
616
617
618/*------------------------------*/
619
620
621
622/*--------------------------------
623** Register: WHO_AM_I
624** Enum: FXOS8700_WHO_AM_I
625** --
626** Offset : 0x0D - Device ID.
627** ------------------------------*/
628typedef uint8_t FXOS8700_WHO_AM_I_t;
629
630
631
632/*--------------------------------
633** Register: XYZ_DATA_CFG
634** Enum: FXOS8700_XYZ_DATA_CFG
635** --
636** Offset : 0x0E - Acceleration dynamic range and filter enable settings.
637** ------------------------------*/
638typedef union {
639 struct {
640 uint8_t fs : 2;
641 uint8_t _reserved_ : 2;
642 uint8_t hpf_out : 1; /* - Enable high-pass filter on acceleration output data */
643
644 } b;
645 uint8_t w;
646} FXOS8700_XYZ_DATA_CFG_t;
647
648
649/*
650** XYZ_DATA_CFG - Bit field mask definitions
651*/
652#define FXOS8700_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03)
653#define FXOS8700_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0)
654
655#define FXOS8700_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10)
656#define FXOS8700_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4)
657
658
659/*
660** XYZ_DATA_CFG - Bit field value definitions
661*/
662#define FXOS8700_XYZ_DATA_CFG_HPF_OUT_EN ((uint8_t) 0x10) /* Enable high-pass filter on acceleration output */
663 /* data */
664#define FXOS8700_XYZ_DATA_CFG_HPF_OUT_DISABLE ((uint8_t) 0x00) /* High-pass filter is disabled */
665#define FXOS8700_XYZ_DATA_CFG_FS_2G_0P244 ((uint8_t) 0x00) /* 0.244 mg/LSB */
666#define FXOS8700_XYZ_DATA_CFG_FS_4G_0P488 ((uint8_t) 0x01) /* 0.488 mg/LSB */
667#define FXOS8700_XYZ_DATA_CFG_FS_8G_0P976 ((uint8_t) 0x02) /* 0.976 mg/LSB */
668/*------------------------------*/
669
670
671
672/*--------------------------------
673** Register: HP_FILTER_CUTOFF
674** Enum: FXOS8700_HP_FILTER_CUTOFF
675** --
676** Offset : 0x0F - Pulse detection highpass and lowpass filter enabling bits.
677** ------------------------------*/
678typedef union {
679 struct {
680 uint8_t sel : 2;
681 uint8_t _reserved_ : 2;
682 uint8_t pulse_lpf_en : 1;
683 uint8_t pulse_hpf_byp : 1;
684 } b;
685 uint8_t w;
686} FXOS8700_HP_FILTER_CUTOFF_t;
687
688
689/*
690** HP_FILTER_CUTOFF - Bit field mask definitions
691*/
692#define FXOS8700_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03)
693#define FXOS8700_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0)
694
695#define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10)
696#define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4)
697
698#define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20)
699#define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5)
700
701
702/*
703** HP_FILTER_CUTOFF - Bit field value definitions
704*/
705#define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_EN ((uint8_t) 0x00) /* HPF enabled for pulse processing */
706#define FXOS8700_HP_FILTER_CUTOFF_PULSE_HPF_BYP_BYPASS ((uint8_t) 0x20) /* HPF bypassed for pulse processing */
707#define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_EN ((uint8_t) 0x10) /* LPF enabled for pulse processing */
708#define FXOS8700_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLE ((uint8_t) 0x00) /* LPF bypassed for pulse processing */
709#define FXOS8700_HP_FILTER_CUTOFF_SEL_EN ((uint8_t) 0x01) /* HPF cutoff frequency selection Enabled */
710#define FXOS8700_HP_FILTER_CUTOFF_SEL_DISABLE ((uint8_t) 0x00) /* HPF cutoff frequency selection Disabled */
711/*------------------------------*/
712
713
714
715/*--------------------------------
716** Register: PL_STATUS
717** Enum: FXOS8700_PL_STATUS
718** --
719** Offset : 0x10 - Landscape/portrait orientation status.
720** ------------------------------*/
721typedef union {
722 struct {
723 uint8_t bafro : 1;
724 uint8_t lapo : 2;
725 uint8_t _reserved_ : 3;
726 uint8_t lo : 1;
727 uint8_t newlp : 1;
728 } b;
729 uint8_t w;
730} FXOS8700_PL_STATUS_t;
731
732
733/*
734** PL_STATUS - Bit field mask definitions
735*/
736#define FXOS8700_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01)
737#define FXOS8700_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0)
738
739#define FXOS8700_PL_STATUS_LAPO_MASK ((uint8_t) 0x06)
740#define FXOS8700_PL_STATUS_LAPO_SHIFT ((uint8_t) 1)
741
742#define FXOS8700_PL_STATUS_LO_MASK ((uint8_t) 0x40)
743#define FXOS8700_PL_STATUS_LO_SHIFT ((uint8_t) 6)
744
745#define FXOS8700_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80)
746#define FXOS8700_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7)
747
748
749/*------------------------------*/
750
751
752
753/*--------------------------------
754** Register: PL_CFG
755** Enum: FXOS8700_PL_CFG
756** --
757** Offset : 0x11 - Landscape/portrait configuration.
758** ------------------------------*/
759typedef union {
760 struct {
761 uint8_t _reserved_ : 6;
762 uint8_t pl_en : 1;
763 uint8_t dbcntm : 1;
764 } b;
765 uint8_t w;
766} FXOS8700_PL_CFG_t;
767
768
769/*
770** PL_CFG - Bit field mask definitions
771*/
772#define FXOS8700_PL_CFG_PL_EN_MASK ((uint8_t) 0x40)
773#define FXOS8700_PL_CFG_PL_EN_SHIFT ((uint8_t) 6)
774
775#define FXOS8700_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80)
776#define FXOS8700_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7)
777
778
779/*
780** PL_CFG - Bit field value definitions
781*/
782#define FXOS8700_PL_CFG_DBCNTM_DECREMENT_MODE ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest is */
783 /* no longer valid */
784#define FXOS8700_PL_CFG_DBCNTM_CLEAR_MODE ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */
785 /* longer valid */
786#define FXOS8700_PL_CFG_PL_EN_DISABLE ((uint8_t) 0x00) /* Portrait/Landscape detection is disabled. */
787#define FXOS8700_PL_CFG_PL_EN_ENABLE ((uint8_t) 0x40) /* Portrait/Landscape detection is enabled. */
788/*------------------------------*/
789
790
791
792/*--------------------------------
793** Register: PL_COUNT
794** Enum: FXOS8700_PL_COUNT
795** --
796** Offset : 0x12 - Landscape/portrait debounce counter.
797** ------------------------------*/
798typedef union {
799 struct {
800 uint8_t dbnce;
801 } b;
802 uint8_t w;
803} FXOS8700_PL_COUNT_t;
804
805
806/*
807** PL_COUNT - Bit field mask definitions
808*/
809#define FXOS8700_PL_COUNT_DBNCE_MASK ((uint8_t) 0xFF)
810#define FXOS8700_PL_COUNT_DBNCE_SHIFT ((uint8_t) 0)
811
812
813/*------------------------------*/
814
815
816
817/*--------------------------------
818** Register: PL_BF_ZCOMP
819** Enum: FXOS8700_PL_BF_ZCOMP
820** --
821** Offset : 0x13 - Back/front trip angle threshold.
822** ------------------------------*/
823typedef union {
824 struct {
825 uint8_t zlock : 3;
826 uint8_t _reserved_ : 3;
827 uint8_t bkfr : 2;
828 } b;
829 uint8_t w;
830} FXOS8700_PL_BF_ZCOMP_t;
831
832
833/*
834** PL_BF_ZCOMP - Bit field mask definitions
835*/
836#define FXOS8700_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07)
837#define FXOS8700_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0)
838
839#define FXOS8700_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0)
840#define FXOS8700_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6)
841
842
843/*
844** PL_BF_ZCOMP - Bit field value definitions
845*/
846#define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT80_GT280__FB_LT260_GT100 ((uint8_t) 0x00)
847#define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT75_GT285__FB_LT255_GT105 ((uint8_t) 0x40)
848#define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT70_GT290__FB_LT250_GT110 ((uint8_t) 0x80)
849#define FXOS8700_PL_BF_ZCOMP_BKFR_BF_LT65_GT295__FB_LT245_GT115 ((uint8_t) 0xc0)
850#define FXOS8700_PL_BF_ZCOMP_ZLOCK_13P6MIN_14P5MAX ((uint8_t) 0x00)
851#define FXOS8700_PL_BF_ZCOMP_ZLOCK_17P1MIN_18P2MAX ((uint8_t) 0x01)
852#define FXOS8700_PL_BF_ZCOMP_ZLOCK_20P7MIN_22P0MAX ((uint8_t) 0x02)
853#define FXOS8700_PL_BF_ZCOMP_ZLOCK_24P4MIN_25P9MAX ((uint8_t) 0x04)
854#define FXOS8700_PL_BF_ZCOMP_ZLOCK_28P1MIN_30P0MAX ((uint8_t) 0x04)
855#define FXOS8700_PL_BF_ZCOMP_ZLOCK_32P0MIN_34P2MAX ((uint8_t) 0x05)
856#define FXOS8700_PL_BF_ZCOMP_ZLOCK_36P1MIN_38P7MAX ((uint8_t) 0x06)
857#define FXOS8700_PL_BF_ZCOMP_ZLOCK_40P4MIN_43P4MAX ((uint8_t) 0x07)
858/*------------------------------*/
859
860
861
862/*--------------------------------
863** Register: PL_THS_REG
864** Enum: FXOS8700_PL_THS_REG
865** --
866** Offset : 0x14 - Portrait to landscape trip threshold angle and hysteresis settings.
867** ------------------------------*/
868typedef union {
869 struct {
870 uint8_t hys : 3;
871 uint8_t pl_ths : 5;
872 } b;
873 uint8_t w;
874} FXOS8700_PL_THS_REG_t;
875
876
877/*
878** PL_THS_REG - Bit field mask definitions
879*/
880#define FXOS8700_PL_THS_REG_HYS_MASK ((uint8_t) 0x07)
881#define FXOS8700_PL_THS_REG_HYS_SHIFT ((uint8_t) 0)
882
883#define FXOS8700_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8)
884#define FXOS8700_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3)
885
886
887/*
888** PL_THS_REG - Bit field value definitions
889*/
890#define FXOS8700_PL_THS_REG_PL_THS_15DEG ((uint8_t) 0x38)
891#define FXOS8700_PL_THS_REG_PL_THS_20DEG ((uint8_t) 0x48)
892#define FXOS8700_PL_THS_REG_PL_THS_30DEG ((uint8_t) 0x60)
893#define FXOS8700_PL_THS_REG_PL_THS_35DEG ((uint8_t) 0x68)
894#define FXOS8700_PL_THS_REG_PL_THS_40DEG ((uint8_t) 0x78)
895#define FXOS8700_PL_THS_REG_PL_THS_45DEG ((uint8_t) 0x80)
896#define FXOS8700_PL_THS_REG_PL_THS_55DEG ((uint8_t) 0x98)
897#define FXOS8700_PL_THS_REG_PL_THS_60DEG ((uint8_t) 0xa0)
898#define FXOS8700_PL_THS_REG_PL_THS_70DEG ((uint8_t) 0xb8)
899#define FXOS8700_PL_THS_REG_PL_THS_75DEG ((uint8_t) 0xc8)
900#define FXOS8700_PL_THS_REG_HYS_LP45_PL45 ((uint8_t) 0x00)
901#define FXOS8700_PL_THS_REG_HYS_LP49_PL41 ((uint8_t) 0x01)
902#define FXOS8700_PL_THS_REG_HYS_LP52_PL38 ((uint8_t) 0x02)
903#define FXOS8700_PL_THS_REG_HYS_LP56_PL34 ((uint8_t) 0x03)
904#define FXOS8700_PL_THS_REG_HYS_LP59_PL31 ((uint8_t) 0x04)
905#define FXOS8700_PL_THS_REG_HYS_LP62_PL28 ((uint8_t) 0x05)
906#define FXOS8700_PL_THS_REG_HYS_LP66_PL24 ((uint8_t) 0x06)
907#define FXOS8700_PL_THS_REG_HYS_LP69_PL21 ((uint8_t) 0x07)
908/*------------------------------*/
909
910
911
912/*--------------------------------
913** Register: A_FFMT_CFG
914** Enum: FXOS8700_A_FFMT_CFG
915** --
916** Offset : 0x15 - Freefall/motion function configuration.
917** ------------------------------*/
918typedef union {
919 struct {
920 uint8_t _reserved_ : 3;
921 uint8_t xefe : 1;
922 uint8_t yefe : 1;
923 uint8_t zefe : 1;
924 uint8_t oae : 1;
925 uint8_t ele : 1;
926 } b;
927 uint8_t w;
928} FXOS8700_A_FFMT_CFG_t;
929
930
931/*
932** A_FFMT_CFG - Bit field mask definitions
933*/
934#define FXOS8700_A_FFMT_CFG_XEFE_MASK ((uint8_t) 0x08)
935#define FXOS8700_A_FFMT_CFG_XEFE_SHIFT ((uint8_t) 3)
936
937#define FXOS8700_A_FFMT_CFG_YEFE_MASK ((uint8_t) 0x10)
938#define FXOS8700_A_FFMT_CFG_YEFE_SHIFT ((uint8_t) 4)
939
940#define FXOS8700_A_FFMT_CFG_ZEFE_MASK ((uint8_t) 0x20)
941#define FXOS8700_A_FFMT_CFG_ZEFE_SHIFT ((uint8_t) 5)
942
943#define FXOS8700_A_FFMT_CFG_OAE_MASK ((uint8_t) 0x40)
944#define FXOS8700_A_FFMT_CFG_OAE_SHIFT ((uint8_t) 6)
945
946#define FXOS8700_A_FFMT_CFG_ELE_MASK ((uint8_t) 0x80)
947#define FXOS8700_A_FFMT_CFG_ELE_SHIFT ((uint8_t) 7)
948
949
950/*
951** A_FFMT_CFG - Bit field value definitions
952*/
953#define FXOS8700_A_FFMT_CFG_ELE_EN ((uint8_t) 0x80) /* Event flag latch enabled */
954#define FXOS8700_A_FFMT_CFG_ELE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
955#define FXOS8700_A_FFMT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall flag */
956#define FXOS8700_A_FFMT_CFG_OAE_MOTION ((uint8_t) 0x40) /* Motion flag */
957#define FXOS8700_A_FFMT_CFG_ZEFE_DIS ((uint8_t) 0x00) /* Event detection disabled */
958#define FXOS8700_A_FFMT_CFG_ZEFE_RAISE_EVENT ((uint8_t) 0x20) /* Raise event flag on measured Z-axis acceleration */
959 /* above/below threshold */
960#define FXOS8700_A_FFMT_CFG_YEFE_DIS ((uint8_t) 0x00) /* Event detection disabled */
961#define FXOS8700_A_FFMT_CFG_YEFE_RAISE_EVENT ((uint8_t) 0x10) /* Raise event flag on measured Y-axis acceleration */
962 /* above/below threshold */
963#define FXOS8700_A_FFMT_CFG_XEFE_DIS ((uint8_t) 0x00) /* Event detection disabled */
964#define FXOS8700_A_FFMT_CFG_XEFE_RAISE_EVENT ((uint8_t) 0x08) /* Raise event flag on measured X-axis acceleration */
965 /* above/below threshold */
966/*------------------------------*/
967
968
969
970/*--------------------------------
971** Register: A_FFMT_SRC
972** Enum: FXOS8700_A_FFMT_SRC
973** --
974** Offset : 0x16 - Freefall/motion event source register.
975** ------------------------------*/
976typedef union {
977 struct {
978 uint8_t xhp : 1;
979 uint8_t xhe : 1;
980 uint8_t yhp : 1;
981 uint8_t yhe : 1;
982 uint8_t zhp : 1;
983 uint8_t zhe : 1;
984 uint8_t _reserved_ : 1;
985 uint8_t ea : 1;
986 } b;
987 uint8_t w;
988} FXOS8700_A_FFMT_SRC_t;
989
990
991/*
992** A_FFMT_SRC - Bit field mask definitions
993*/
994#define FXOS8700_A_FFMT_SRC_XHP_MASK ((uint8_t) 0x01)
995#define FXOS8700_A_FFMT_SRC_XHP_SHIFT ((uint8_t) 0)
996
997#define FXOS8700_A_FFMT_SRC_XHE_MASK ((uint8_t) 0x02)
998#define FXOS8700_A_FFMT_SRC_XHE_SHIFT ((uint8_t) 1)
999
1000#define FXOS8700_A_FFMT_SRC_YHP_MASK ((uint8_t) 0x04)
1001#define FXOS8700_A_FFMT_SRC_YHP_SHIFT ((uint8_t) 2)
1002
1003#define FXOS8700_A_FFMT_SRC_YHE_MASK ((uint8_t) 0x08)
1004#define FXOS8700_A_FFMT_SRC_YHE_SHIFT ((uint8_t) 3)
1005
1006#define FXOS8700_A_FFMT_SRC_ZHP_MASK ((uint8_t) 0x10)
1007#define FXOS8700_A_FFMT_SRC_ZHP_SHIFT ((uint8_t) 4)
1008
1009#define FXOS8700_A_FFMT_SRC_ZHE_MASK ((uint8_t) 0x20)
1010#define FXOS8700_A_FFMT_SRC_ZHE_SHIFT ((uint8_t) 5)
1011
1012#define FXOS8700_A_FFMT_SRC_EA_MASK ((uint8_t) 0x80)
1013#define FXOS8700_A_FFMT_SRC_EA_SHIFT ((uint8_t) 7)
1014
1015
1016/*------------------------------*/
1017
1018
1019
1020/*--------------------------------
1021** Register: A_FFMT_THS
1022** Enum: FXOS8700_A_FFMT_THS
1023** --
1024** Offset : 0x17 - Freefall/motion threshold register.
1025** ------------------------------*/
1026typedef union {
1027 struct {
1028 uint8_t ths : 7;
1029 uint8_t dbcntm : 1;
1030 } b;
1031 uint8_t w;
1032} FXOS8700_A_FFMT_THS_t;
1033
1034
1035/*
1036** A_FFMT_THS - Bit field mask definitions
1037*/
1038#define FXOS8700_A_FFMT_THS_THS_MASK ((uint8_t) 0x7F)
1039#define FXOS8700_A_FFMT_THS_THS_SHIFT ((uint8_t) 0)
1040
1041#define FXOS8700_A_FFMT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1042#define FXOS8700_A_FFMT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1043
1044
1045/*------------------------------*/
1046
1047
1048
1049/*--------------------------------
1050** Register: A_FFMT_COUNT
1051** Enum: FXOS8700_A_FFMT_COUNT
1052** --
1053** Offset : 0x18 - Freefall/motion debounce counter.
1054** ------------------------------*/
1055typedef uint8_t FXOS8700_A_FFMT_COUNT_t;
1056
1057
1058
1059
1060/*--------------------------------
1061** Register: TRANSIENT_CFG
1062** Enum: FXOS8700_TRANSIENT_CFG
1063** --
1064** Offset : 0x1D - Transient function configuration.
1065** ------------------------------*/
1066typedef union {
1067 struct {
1068 uint8_t hpf_byp : 1;
1069 uint8_t xtefe : 1;
1070 uint8_t ytefe : 1;
1071 uint8_t ztefe : 1;
1072 uint8_t tele : 1;
1073 } b;
1074 uint8_t w;
1075} FXOS8700_TRANSIENT_CFG_t;
1076
1077
1078/*
1079** TRANSIENT_CFG - Bit field mask definitions
1080*/
1081#define FXOS8700_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01)
1082#define FXOS8700_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0)
1083
1084#define FXOS8700_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02)
1085#define FXOS8700_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1)
1086
1087#define FXOS8700_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04)
1088#define FXOS8700_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2)
1089
1090#define FXOS8700_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08)
1091#define FXOS8700_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3)
1092
1093#define FXOS8700_TRANSIENT_CFG_TELE_MASK ((uint8_t) 0x10)
1094#define FXOS8700_TRANSIENT_CFG_TELE_SHIFT ((uint8_t) 4)
1095
1096
1097/*
1098** TRANSIENT_CFG - Bit field value definitions
1099*/
1100#define FXOS8700_TRANSIENT_CFG_TELE_EN ((uint8_t) 0x10) /* Event flag latch enabled: the transient */
1101 /* interrupt event flag is latched and a read of */
1102 /* the TRANSIENT_SRC register is required to */
1103 /* clear the event flag */
1104#define FXOS8700_TRANSIENT_CFG_TELE_DIS ((uint8_t) 0x00) /* Event flag latch disabled: the transient */
1105 /* interrupt flag reflects the real-time status */
1106 /* of the function */
1107#define FXOS8700_TRANSIENT_CFG_ZTEFE_EN ((uint8_t) 0x08) /* Z-axis event detection enabled. Raise event */
1108 /* flag on Z-axis acceleration value greater than */
1109 /* threshold */
1110#define FXOS8700_TRANSIENT_CFG_ZTEFE_DIS ((uint8_t) 0x00) /* Z-axis event detection disabled */
1111#define FXOS8700_TRANSIENT_CFG_YTEFE_EN ((uint8_t) 0x04) /* Y-axis event detection enabled. Raise event */
1112 /* flag on Y-axis acceleration value greater than */
1113 /* threshold */
1114#define FXOS8700_TRANSIENT_CFG_YTEFE_DIS ((uint8_t) 0x00) /* Y-axis event detection disabled */
1115#define FXOS8700_TRANSIENT_CFG_XTEFE_EN ((uint8_t) 0x02) /* X-axis event detection enabled. Raise event */
1116 /* flag on X-axis acceleration value greater than */
1117 /* threshold */
1118#define FXOS8700_TRANSIENT_CFG_XTEFE_DIS ((uint8_t) 0x00) /* X-axis event detection disabled */
1119#define FXOS8700_TRANSIENT_CFG_HPF_BYP_EN ((uint8_t) 0x01) /* High-pass filter is not applied to */
1120 /* accelerometer data input to the transient */
1121 /* function */
1122#define FXOS8700_TRANSIENT_CFG_HPF_BYP_DIS ((uint8_t) 0x00) /* High-pass filter is applied to accelerometer */
1123 /* data input to the transient function */
1124/*------------------------------*/
1125
1126
1127
1128/*--------------------------------
1129** Register: TRANSIENT_SRC
1130** Enum: FXOS8700_TRANSIENT_SRC
1131** --
1132** Offset : 0x1E - Transient event status register.
1133** ------------------------------*/
1134typedef union {
1135 struct {
1136 uint8_t trans_xpol : 1;
1137 uint8_t tran_xef : 1;
1138 uint8_t tran_ypol : 1;
1139 uint8_t tran_yef : 1;
1140 uint8_t tran_zpol : 1;
1141 uint8_t tran_zef : 1;
1142 uint8_t tran_ea : 1;
1143 } b;
1144 uint8_t w;
1145} FXOS8700_TRANSIENT_SRC_t;
1146
1147
1148/*
1149** TRANSIENT_SRC - Bit field mask definitions
1150*/
1151#define FXOS8700_TRANSIENT_SRC_TRANS_XPOL_MASK ((uint8_t) 0x01)
1152#define FXOS8700_TRANSIENT_SRC_TRANS_XPOL_SHIFT ((uint8_t) 0)
1153
1154#define FXOS8700_TRANSIENT_SRC_TRAN_XEF_MASK ((uint8_t) 0x02)
1155#define FXOS8700_TRANSIENT_SRC_TRAN_XEF_SHIFT ((uint8_t) 1)
1156
1157#define FXOS8700_TRANSIENT_SRC_TRAN_YPOL_MASK ((uint8_t) 0x04)
1158#define FXOS8700_TRANSIENT_SRC_TRAN_YPOL_SHIFT ((uint8_t) 2)
1159
1160#define FXOS8700_TRANSIENT_SRC_TRAN_YEF_MASK ((uint8_t) 0x08)
1161#define FXOS8700_TRANSIENT_SRC_TRAN_YEF_SHIFT ((uint8_t) 3)
1162
1163#define FXOS8700_TRANSIENT_SRC_TRAN_ZPOL_MASK ((uint8_t) 0x10)
1164#define FXOS8700_TRANSIENT_SRC_TRAN_ZPOL_SHIFT ((uint8_t) 4)
1165
1166#define FXOS8700_TRANSIENT_SRC_TRAN_ZEF_MASK ((uint8_t) 0x20)
1167#define FXOS8700_TRANSIENT_SRC_TRAN_ZEF_SHIFT ((uint8_t) 5)
1168
1169#define FXOS8700_TRANSIENT_SRC_TRAN_EA_MASK ((uint8_t) 0x40)
1170#define FXOS8700_TRANSIENT_SRC_TRAN_EA_SHIFT ((uint8_t) 6)
1171
1172
1173/*------------------------------*/
1174
1175
1176
1177/*--------------------------------
1178** Register: TRANSIENT_THS
1179** Enum: FXOS8700_TRANSIENT_THS
1180** --
1181** Offset : 0x1F - Transient event threshold.
1182** ------------------------------*/
1183typedef union {
1184 struct {
1185 uint8_t tr_ths : 7;
1186 uint8_t tr_dbcntm : 1;
1187 } b;
1188 uint8_t w;
1189} FXOS8700_TRANSIENT_THS_t;
1190
1191
1192/*
1193** TRANSIENT_THS - Bit field mask definitions
1194*/
1195#define FXOS8700_TRANSIENT_THS_TR_THS_MASK ((uint8_t) 0x7F)
1196#define FXOS8700_TRANSIENT_THS_TR_THS_SHIFT ((uint8_t) 0)
1197
1198#define FXOS8700_TRANSIENT_THS_TR_DBCNTM_MASK ((uint8_t) 0x80)
1199#define FXOS8700_TRANSIENT_THS_TR_DBCNTM_SHIFT ((uint8_t) 7)
1200
1201
1202/*
1203** TRANSIENT_THS - Bit field value definitions
1204*/
1205#define FXOS8700_TRANSIENT_THS_TR_THS_DECREMENTS ((uint8_t) 0x00) /* Decrements debounce counter when the transient */
1206 /* event condition is not true during the current */
1207 /* ODR period */
1208#define FXOS8700_TRANSIENT_THS_TR_THS_CLEAR ((uint8_t) 0x01) /* Clears debounce counter when the transient */
1209 /* event condition is not true during the current */
1210 /* ODR period */
1211/*------------------------------*/
1212
1213
1214
1215/*--------------------------------
1216** Register: TRANSIENT_COUNT
1217** Enum: FXOS8700_TRANSIENT_COUNT
1218** --
1219** Offset : 0x20 - Transient debounce counter.
1220** ------------------------------*/
1221typedef uint8_t FXOS8700_TRANSIENT_COUNT_t;
1222
1223
1224
1225
1226
1227/*--------------------------------
1228** Register: PULSE_CFG
1229** Enum: FXOS8700_PULSE_CFG
1230** --
1231** Offset : 0x21 - Pulse function configuration.
1232** ------------------------------*/
1233typedef union {
1234 struct {
1235 uint8_t pls_xspefe : 1;
1236 uint8_t pls_xdpefe : 1;
1237 uint8_t pls_yspefe : 1;
1238 uint8_t pls_ydpefe : 1;
1239 uint8_t pls_zspefe : 1;
1240 uint8_t pls_zdpefe : 1;
1241 uint8_t pls_ele : 1;
1242 uint8_t pls_dpa : 1;
1243 } b;
1244 uint8_t w;
1245} FXOS8700_PULSE_CFG_t;
1246
1247
1248/*
1249** PULSE_CFG - Bit field mask definitions
1250*/
1251#define FXOS8700_PULSE_CFG_PLS_XSPEFE_MASK ((uint8_t) 0x01)
1252#define FXOS8700_PULSE_CFG_PLS_XSPEFE_SHIFT ((uint8_t) 0)
1253
1254#define FXOS8700_PULSE_CFG_PLS_XDPEFE_MASK ((uint8_t) 0x02)
1255#define FXOS8700_PULSE_CFG_PLS_XDPEFE_SHIFT ((uint8_t) 1)
1256
1257#define FXOS8700_PULSE_CFG_PLS_YSPEFE_MASK ((uint8_t) 0x04)
1258#define FXOS8700_PULSE_CFG_PLS_YSPEFE_SHIFT ((uint8_t) 2)
1259
1260#define FXOS8700_PULSE_CFG_PLS_YDPEFE_MASK ((uint8_t) 0x08)
1261#define FXOS8700_PULSE_CFG_PLS_YDPEFE_SHIFT ((uint8_t) 3)
1262
1263#define FXOS8700_PULSE_CFG_PLS_ZSPEFE_MASK ((uint8_t) 0x10)
1264#define FXOS8700_PULSE_CFG_PLS_ZSPEFE_SHIFT ((uint8_t) 4)
1265
1266#define FXOS8700_PULSE_CFG_PLS_ZDPEFE_MASK ((uint8_t) 0x20)
1267#define FXOS8700_PULSE_CFG_PLS_ZDPEFE_SHIFT ((uint8_t) 5)
1268
1269#define FXOS8700_PULSE_CFG_PLS_ELE_MASK ((uint8_t) 0x40)
1270#define FXOS8700_PULSE_CFG_PLS_ELE_SHIFT ((uint8_t) 6)
1271
1272#define FXOS8700_PULSE_CFG_PLS_DPA_MASK ((uint8_t) 0x80)
1273#define FXOS8700_PULSE_CFG_PLS_DPA_SHIFT ((uint8_t) 7)
1274
1275
1276/*
1277** PULSE_CFG - Bit field value definitions
1278*/
1279#define FXOS8700_PULSE_CFG_PLS_DPA_DIS ((uint8_t) 0x00) /* Setting the pls_dpa bit momentarily suspends the */
1280 /* double-tap detection if the start of a pulse is */
1281 /* detected during the time period specified by the */
1282 /* PULSE_LTCY register and the pulse ends before the */
1283 /* end of the time period specified by the PULSE_LTCY */
1284 /* register */
1285#define FXOS8700_PULSE_CFG_PLS_DPA_EN ((uint8_t) 0x80) /* Double-pulse detection is not aborted if the start */
1286 /* of a pulse is detected during the time period */
1287 /* specified by the PULSE_LTCY register */
1288#define FXOS8700_PULSE_CFG_PLS_ELE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1289#define FXOS8700_PULSE_CFG_PLS_ELE_EN ((uint8_t) 0x40) /* Event flag latch enabled */
1290#define FXOS8700_PULSE_CFG_PLS_ZDPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1291#define FXOS8700_PULSE_CFG_PLS_ZDPEFE_EN ((uint8_t) 0x20) /* Raise event flag on detection of double-pulse */
1292 /* event on Z-axis */
1293#define FXOS8700_PULSE_CFG_PLS_ZSPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1294#define FXOS8700_PULSE_CFG_PLS_ZSPEFE_EN ((uint8_t) 0x10) /* Raise event flag on detection of single-pulse */
1295 /* event on Z-axis */
1296#define FXOS8700_PULSE_CFG_PLS_YDPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1297#define FXOS8700_PULSE_CFG_PLS_YDPEFE_EN ((uint8_t) 0x08) /* Raise event flag on detection of double-pulse */
1298 /* event on Y-axis */
1299#define FXOS8700_PULSE_CFG_PLS_YSPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1300#define FXOS8700_PULSE_CFG_PLS_YSPEFE_EN ((uint8_t) 0x04) /* Raise event flag on detection of single-pulse */
1301 /* event on Y-axis */
1302#define FXOS8700_PULSE_CFG_PLS_XDPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1303#define FXOS8700_PULSE_CFG_PLS_XDPEFE_EN ((uint8_t) 0x02) /* Raise event flag on detection of double-pulse */
1304 /* event on X-axis */
1305#define FXOS8700_PULSE_CFG_PLS_XSPEFE_DIS ((uint8_t) 0x00) /* Event flag latch disabled */
1306#define FXOS8700_PULSE_CFG_PLS_XSPEFE_EN ((uint8_t) 0x01) /* Raise event flag on detection of single-pulse */
1307 /* event on X-axis */
1308/*------------------------------*/
1309
1310
1311
1312/*--------------------------------
1313** Register: PULSE_SRC
1314** Enum: FXOS8700_PULSE_SRC
1315** --
1316** Offset : 0x22 - Pulse function source register.
1317** ------------------------------*/
1318typedef union {
1319 struct {
1320 uint8_t pls_src_polx : 1;
1321 uint8_t pls_src_poly : 1;
1322 uint8_t pls_src_polz : 1;
1323 uint8_t pls_src_dpe : 1;
1324 uint8_t pls_src_axx : 1;
1325 uint8_t pls_src_axy : 1;
1326 uint8_t pls_src_axz : 1;
1327 uint8_t pls_src_ea : 1;
1328 } b;
1329 uint8_t w;
1330} FXOS8700_PULSE_SRC_t;
1331
1332
1333/*
1334** PULSE_SRC - Bit field mask definitions
1335*/
1336#define FXOS8700_PULSE_SRC_PLS_SRC_POLX_MASK ((uint8_t) 0x01)
1337#define FXOS8700_PULSE_SRC_PLS_SRC_POLX_SHIFT ((uint8_t) 0)
1338
1339#define FXOS8700_PULSE_SRC_PLS_SRC_POLY_MASK ((uint8_t) 0x02)
1340#define FXOS8700_PULSE_SRC_PLS_SRC_POLY_SHIFT ((uint8_t) 1)
1341
1342#define FXOS8700_PULSE_SRC_PLS_SRC_POLZ_MASK ((uint8_t) 0x04)
1343#define FXOS8700_PULSE_SRC_PLS_SRC_POLZ_SHIFT ((uint8_t) 2)
1344
1345#define FXOS8700_PULSE_SRC_PLS_SRC_DPE_MASK ((uint8_t) 0x08)
1346#define FXOS8700_PULSE_SRC_PLS_SRC_DPE_SHIFT ((uint8_t) 3)
1347
1348#define FXOS8700_PULSE_SRC_PLS_SRC_AXX_MASK ((uint8_t) 0x10)
1349#define FXOS8700_PULSE_SRC_PLS_SRC_AXX_SHIFT ((uint8_t) 4)
1350
1351#define FXOS8700_PULSE_SRC_PLS_SRC_AXY_MASK ((uint8_t) 0x20)
1352#define FXOS8700_PULSE_SRC_PLS_SRC_AXY_SHIFT ((uint8_t) 5)
1353
1354#define FXOS8700_PULSE_SRC_PLS_SRC_AXZ_MASK ((uint8_t) 0x40)
1355#define FXOS8700_PULSE_SRC_PLS_SRC_AXZ_SHIFT ((uint8_t) 6)
1356
1357#define FXOS8700_PULSE_SRC_PLS_SRC_EA_MASK ((uint8_t) 0x80)
1358#define FXOS8700_PULSE_SRC_PLS_SRC_EA_SHIFT ((uint8_t) 7)
1359
1360
1361/*------------------------------*/
1362
1363
1364
1365/*--------------------------------
1366** Register: PULSE_THSX
1367** Enum: FXOS8700_PULSE_THSX
1368** --
1369** Offset : 0x23 - X-axis pulse threshold.
1370** ------------------------------*/
1371typedef union {
1372 struct {
1373 uint8_t pls_thsx : 7;
1374 } b;
1375 uint8_t w;
1376} FXOS8700_PULSE_THSX_t;
1377
1378
1379/*
1380** PULSE_THSX - Bit field mask definitions
1381*/
1382#define FXOS8700_PULSE_THSX_PLS_THSX_MASK ((uint8_t) 0x7F)
1383#define FXOS8700_PULSE_THSX_PLS_THSX_SHIFT ((uint8_t) 0)
1384
1385
1386/*------------------------------*/
1387
1388
1389
1390/*--------------------------------
1391** Register: PULSE_THSY
1392** Enum: FXOS8700_PULSE_THSY
1393** --
1394** Offset : 0x24 - Y-axis pulse threshold.
1395** ------------------------------*/
1396typedef union {
1397 struct {
1398 uint8_t pls_thsy : 7;
1399 } b;
1400 uint8_t w;
1401} FXOS8700_PULSE_THSY_t;
1402
1403
1404/*
1405** PULSE_THSY - Bit field mask definitions
1406*/
1407#define FXOS8700_PULSE_THSY_PLS_THSY_MASK ((uint8_t) 0x7F)
1408#define FXOS8700_PULSE_THSY_PLS_THSY_SHIFT ((uint8_t) 0)
1409
1410
1411/*------------------------------*/
1412
1413
1414
1415/*--------------------------------
1416** Register: PULSE_THSZ
1417** Enum: FXOS8700_PULSE_THSZ
1418** --
1419** Offset : 0x25 - Z-axis pulse threshold.
1420** ------------------------------*/
1421typedef union {
1422 struct {
1423 uint8_t pls_thsz : 7;
1424 } b;
1425 uint8_t w;
1426} FXOS8700_PULSE_THSZ_t;
1427
1428
1429/*
1430** PULSE_THSZ - Bit field mask definitions
1431*/
1432#define FXOS8700_PULSE_THSZ_PLS_THSZ_MASK ((uint8_t) 0x7F)
1433#define FXOS8700_PULSE_THSZ_PLS_THSZ_SHIFT ((uint8_t) 0)
1434
1435
1436/*------------------------------*/
1437
1438
1439
1440/*--------------------------------
1441** Register: PULSE_TMLT
1442** Enum: FXOS8700_PULSE_TMLT
1443** --
1444** Offset : 0x26 - Time limit for pulse detection.
1445** ------------------------------*/
1446typedef uint8_t FXOS8700_PULSE_TMLT_t;
1447
1448
1449
1450/*--------------------------------
1451** Register: PULSE_LTCY
1452** Enum: FXOS8700_PULSE_LTCY
1453** --
1454** Offset : 0x27 - Latency time for second pulse detection.
1455** ------------------------------*/
1456typedef uint8_t FXOS8700_PULSE_LTCY_t;
1457
1458
1459/*--------------------------------
1460** Register: PULSE_WIND
1461** Enum: FXOS8700_PULSE_WIND
1462** --
1463** Offset : 0x28 - Window time for second pulse detection.
1464** ------------------------------*/
1465typedef uint8_t FXOS8700_PULSE_WIND_t;
1466
1467
1468
1469/*--------------------------------
1470** Register: ASLP_COUNT
1471** Enum: FXOS8700_ASLP_COUNT
1472** --
1473** Offset : 0x29 - The counter setting for auto-sleep period.
1474** ------------------------------*/
1475typedef uint8_t FXOS8700_ASLP_COUNT_t;
1476
1477
1478
1479/*--------------------------------
1480** Register: CTRL_REG1
1481** Enum: FXOS8700_CTRL_REG1
1482** --
1483** Offset : 0x2A - System ODR, accelerometer OSR (Output sample rate), operating mode.
1484** ------------------------------*/
1485typedef union {
1486 struct {
1487 uint8_t active : 1;
1488 uint8_t f_read : 1;
1489 uint8_t lnoise : 1;
1490 uint8_t dr : 3;
1491 uint8_t aslp_rate : 2;
1492 } b;
1493 uint8_t w;
1494} FXOS8700_CTRL_REG1_t;
1495
1496
1497/*
1498** CTRL_REG1 - Bit field mask definitions
1499*/
1500#define FXOS8700_CTRL_REG1_ACTIVE_MASK ((uint8_t) 0x01)
1501#define FXOS8700_CTRL_REG1_ACTIVE_SHIFT ((uint8_t) 0)
1502
1503#define FXOS8700_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02)
1504#define FXOS8700_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1)
1505
1506#define FXOS8700_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04)
1507#define FXOS8700_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2)
1508
1509#define FXOS8700_CTRL_REG1_DR_MASK ((uint8_t) 0x38)
1510#define FXOS8700_CTRL_REG1_DR_SHIFT ((uint8_t) 3)
1511
1512#define FXOS8700_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0)
1513#define FXOS8700_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6)
1514
1515
1516/*
1517** CTRL_REG1 - Bit field value definitions
1518*/
1519#define FXOS8700_CTRL_REG1_ASLP_RATE_50_HZ ((uint8_t) 0x00)
1520#define FXOS8700_CTRL_REG1_ASLP_RATE_12P5_HZ ((uint8_t) 0x40)
1521#define FXOS8700_CTRL_REG1_ASLP_RATE_6P25_HZ ((uint8_t) 0x80)
1522#define FXOS8700_CTRL_REG1_ASLP_RATE_1P56_HZ ((uint8_t) 0xc0)
1523#define FXOS8700_CTRL_REG1_DR_SINGLE_800_HZ ((uint8_t) 0x00)
1524#define FXOS8700_CTRL_REG1_DR_SINGLE_400_HZ ((uint8_t) 0x08)
1525#define FXOS8700_CTRL_REG1_DR_SINGLE_200_HZ ((uint8_t) 0x10)
1526#define FXOS8700_CTRL_REG1_DR_SINGLE_100_HZ ((uint8_t) 0x18)
1527#define FXOS8700_CTRL_REG1_DR_SINGLE_50_HZ ((uint8_t) 0x20)
1528#define FXOS8700_CTRL_REG1_DR_SINGLE_12P5_HZ ((uint8_t) 0x28)
1529#define FXOS8700_CTRL_REG1_DR_SINGLE_6P25_HZ ((uint8_t) 0x30)
1530#define FXOS8700_CTRL_REG1_DR_SINGLE_1P5625_HZ ((uint8_t) 0x38)
1531#define FXOS8700_CTRL_REG1_DR_HYBRID_400_HZ ((uint8_t) 0x00)
1532#define FXOS8700_CTRL_REG1_DR_HYBRID_200_HZ ((uint8_t) 0x08)
1533#define FXOS8700_CTRL_REG1_DR_HYBRID_100_HZ ((uint8_t) 0x10)
1534#define FXOS8700_CTRL_REG1_DR_HYBRID_50_HZ ((uint8_t) 0x18)
1535#define FXOS8700_CTRL_REG1_DR_HYBRID_25_HZ ((uint8_t) 0x20)
1536#define FXOS8700_CTRL_REG1_DR_HYBRID_6P25_HZ ((uint8_t) 0x28)
1537#define FXOS8700_CTRL_REG1_DR_HYBRID_3P125_HZ ((uint8_t) 0x30)
1538#define FXOS8700_CTRL_REG1_DR_HYBRID_0P7813_HZ ((uint8_t) 0x38)
1539#define FXOS8700_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode */
1540#define FXOS8700_CTRL_REG1_LNOISE_REDUCED_NOISE ((uint8_t) 0x04) /* Reduced noise mode; Note that the FSR setting is */
1541 /* restricted to ±2 g or ±4 g mode. This feature */
1542 /* cannot be used in ±8 g mode */
1543#define FXOS8700_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode */
1544#define FXOS8700_CTRL_REG1_F_READ_FAST ((uint8_t) 0x02) /* Fast-read mode */
1545#define FXOS8700_CTRL_REG1_ACTIVE_ACTIVE_MODE ((uint8_t) 0x01) /* Active mode */
1546#define FXOS8700_CTRL_REG1_ACTIVE_STANDBY_MODE ((uint8_t) 0x00) /* Standby mode */
1547/*------------------------------*/
1548
1549
1550
1551/*--------------------------------
1552** Register: CTRL_REG2
1553** Enum: FXOS8700_CTRL_REG2
1554** --
1555** Offset : 0x2B - Self-test, reset, accelerometer OSR, and sleep mode settings.
1556** ------------------------------*/
1557typedef union {
1558 struct {
1559 uint8_t mods : 2;
1560 uint8_t slpe : 1;
1561 uint8_t smods : 2;
1562 uint8_t _reserved_ : 1;
1563 uint8_t rst : 1;
1564 uint8_t st : 1;
1565 } b;
1566 uint8_t w;
1567} FXOS8700_CTRL_REG2_t;
1568
1569
1570/*
1571** CTRL_REG2 - Bit field mask definitions
1572*/
1573#define FXOS8700_CTRL_REG2_MODS_MASK ((uint8_t) 0x03)
1574#define FXOS8700_CTRL_REG2_MODS_SHIFT ((uint8_t) 0)
1575
1576#define FXOS8700_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04)
1577#define FXOS8700_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2)
1578
1579#define FXOS8700_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18)
1580#define FXOS8700_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3)
1581
1582#define FXOS8700_CTRL_REG2_RST_MASK ((uint8_t) 0x40)
1583#define FXOS8700_CTRL_REG2_RST_SHIFT ((uint8_t) 6)
1584
1585#define FXOS8700_CTRL_REG2_ST_MASK ((uint8_t) 0x80)
1586#define FXOS8700_CTRL_REG2_ST_SHIFT ((uint8_t) 7)
1587
1588
1589/*
1590** CTRL_REG2 - Bit field value definitions
1591*/
1592#define FXOS8700_CTRL_REG2_ST_DIS ((uint8_t) 0x00) /* Self-test disabled */
1593#define FXOS8700_CTRL_REG2_ST_EN ((uint8_t) 0x80) /* Self-test enabled */
1594#define FXOS8700_CTRL_REG2_RST_EN ((uint8_t) 0x40) /* Device reset enabled */
1595#define FXOS8700_CTRL_REG2_RST_DIS ((uint8_t) 0x00) /* Device reset disabled */
1596#define FXOS8700_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00)
1597#define FXOS8700_CTRL_REG2_SMODS_LOW_NOISE_LOW_POWER ((uint8_t) 0x08)
1598#define FXOS8700_CTRL_REG2_SMODS_HIGH_RES ((uint8_t) 0x10)
1599#define FXOS8700_CTRL_REG2_SMODS_LOW_POWER ((uint8_t) 0x18)
1600#define FXOS8700_CTRL_REG2_SLPE_EN ((uint8_t) 0x04)
1601#define FXOS8700_CTRL_REG2_SLPE_DISABLE ((uint8_t) 0x00)
1602#define FXOS8700_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00)
1603#define FXOS8700_CTRL_REG2_MODS_LOW_NOISE_LOW_POWER ((uint8_t) 0x01)
1604#define FXOS8700_CTRL_REG2_MODS_HIGH_RES ((uint8_t) 0x02)
1605#define FXOS8700_CTRL_REG2_MODS_LOW_POWER ((uint8_t) 0x03)
1606/*------------------------------*/
1607
1608
1609
1610/*--------------------------------
1611** Register: CTRL_REG3
1612** Enum: FXOS8700_CTRL_REG3
1613** --
1614** Offset : 0x2C - Sleep mode interrupt wake enable, interrupt polarity, push-pull/open drain configuration.
1615** ------------------------------*/
1616typedef union {
1617 struct {
1618 uint8_t pp_od : 1;
1619 uint8_t ipol : 1;
1620 uint8_t wake_a_vecm : 1;
1621 uint8_t wake_ffmt : 1;
1622 uint8_t wake_pulse : 1;
1623 uint8_t wake_lndprt : 1;
1624 uint8_t wake_trans : 1;
1625 uint8_t fifo_gate : 1;
1626 } b;
1627 uint8_t w;
1628} FXOS8700_CTRL_REG3_t;
1629
1630
1631/*
1632** CTRL_REG3 - Bit field mask definitions
1633*/
1634#define FXOS8700_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01)
1635#define FXOS8700_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0)
1636
1637#define FXOS8700_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02)
1638#define FXOS8700_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1)
1639
1640#define FXOS8700_CTRL_REG3_WAKE_A_VECM_MASK ((uint8_t) 0x04)
1641#define FXOS8700_CTRL_REG3_WAKE_A_VECM_SHIFT ((uint8_t) 2)
1642
1643#define FXOS8700_CTRL_REG3_WAKE_FFMT_MASK ((uint8_t) 0x08)
1644#define FXOS8700_CTRL_REG3_WAKE_FFMT_SHIFT ((uint8_t) 3)
1645
1646#define FXOS8700_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10)
1647#define FXOS8700_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4)
1648
1649#define FXOS8700_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20)
1650#define FXOS8700_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5)
1651
1652#define FXOS8700_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40)
1653#define FXOS8700_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6)
1654
1655#define FXOS8700_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80)
1656#define FXOS8700_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7)
1657
1658
1659/*
1660** CTRL_REG3 - Bit field value definitions
1661*/
1662#define FXOS8700_CTRL_REG3_FIFO_GATE_BYPASSED ((uint8_t) 0x00) /* FIFO gate is bypassed */
1663#define FXOS8700_CTRL_REG3_FIFO_GATE_BLOCKED ((uint8_t) 0x80) /* The FIFO input buffer is blocked from accepting */
1664 /* new samples when transitioning from wake-to-sleep */
1665 /* mode or from sleep-to-wake mode until the FIFO is */
1666 /* flushed */
1667#define FXOS8700_CTRL_REG3_WAKE_TRANS_DIS ((uint8_t) 0x00) /* Transient function is disabled in sleep mode */
1668#define FXOS8700_CTRL_REG3_WAKE_TRANS_EN ((uint8_t) 0x40) /* Transient function is enabled in sleep mode and */
1669 /* can generate an interrupt to wake the system */
1670#define FXOS8700_CTRL_REG3_WAKE_LNDPRT_DIS ((uint8_t) 0x00) /* Orientation function is disabled sleep mode */
1671#define FXOS8700_CTRL_REG3_WAKE_LNDPRT_EN ((uint8_t) 0x20) /* Orientation function is enabled in sleep mode and */
1672 /* can generate an interrupt to wake the system */
1673#define FXOS8700_CTRL_REG3_WAKE_PULSE_DIS ((uint8_t) 0x00) /* Pulse function is disabled in sleep mode */
1674#define FXOS8700_CTRL_REG3_WAKE_PULSE_EN ((uint8_t) 0x10) /* Pulse function is enabled in sleep mode and can */
1675 /* generate an interrupt to wake the system */
1676#define FXOS8700_CTRL_REG3_WAKE_FFMT_DIS ((uint8_t) 0x00) /* Freefall/motion function is disabled in sleep mode */
1677#define FXOS8700_CTRL_REG3_WAKE_FFMT_EN ((uint8_t) 0x08) /* Freefall/motion function is enabled in sleep mode */
1678 /* and can generate an interrupt to wake the system */
1679#define FXOS8700_CTRL_REG3_WAKE_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude function is disabled */
1680 /* in sleep mode */
1681#define FXOS8700_CTRL_REG3_WAKE_A_VECM_EN ((uint8_t) 0x04) /* Acceleration vector-magnitude function is enabled */
1682 /* in sleep mode and can generate an interrupt to */
1683 /* wake the system */
1684#define FXOS8700_CTRL_REG3_IPOL_ACTIVE_LOW ((uint8_t) 0x00) /* Active Low */
1685#define FXOS8700_CTRL_REG3_IPOL_ACTIVE_HIGH ((uint8_t) 0x02) /* Active High */
1686#define FXOS8700_CTRL_REG3_PP_OD_PUSH_PULL ((uint8_t) 0x00) /* Push-pull */
1687#define FXOS8700_CTRL_REG3_PP_OD_OPEN_DRAIN ((uint8_t) 0x01) /* Open Drain */
1688/*------------------------------*/
1689
1690
1691
1692/*--------------------------------
1693** Register: CTRL_REG4
1694** Enum: FXOS8700_CTRL_REG4
1695** --
1696** Offset : 0x2D - Interrupt enable register.
1697** ------------------------------*/
1698typedef union {
1699 struct {
1700 uint8_t int_en_drdy : 1;
1701 uint8_t int_en_a_vecm : 1;
1702 uint8_t int_en_ffmt : 1;
1703 uint8_t int_en_pulse : 1;
1704 uint8_t int_en_lndprt : 1;
1705 uint8_t int_en_trans : 1;
1706 uint8_t int_en_fifo : 1;
1707 uint8_t int_en_aslp : 1;
1708 } b;
1709 uint8_t w;
1710} FXOS8700_CTRL_REG4_t;
1711
1712
1713/*
1714** CTRL_REG4 - Bit field mask definitions
1715*/
1716#define FXOS8700_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01)
1717#define FXOS8700_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0)
1718
1719#define FXOS8700_CTRL_REG4_INT_EN_A_VECM_MASK ((uint8_t) 0x02)
1720#define FXOS8700_CTRL_REG4_INT_EN_A_VECM_SHIFT ((uint8_t) 1)
1721
1722#define FXOS8700_CTRL_REG4_INT_EN_FFMT_MASK ((uint8_t) 0x04)
1723#define FXOS8700_CTRL_REG4_INT_EN_FFMT_SHIFT ((uint8_t) 2)
1724
1725#define FXOS8700_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08)
1726#define FXOS8700_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3)
1727
1728#define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10)
1729#define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4)
1730
1731#define FXOS8700_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20)
1732#define FXOS8700_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5)
1733
1734#define FXOS8700_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1735#define FXOS8700_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1736
1737#define FXOS8700_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80)
1738#define FXOS8700_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7)
1739
1740
1741/*
1742** CTRL_REG4 - Bit field value definitions
1743*/
1744#define FXOS8700_CTRL_REG4_INT_EN_ASLP_DIS ((uint8_t) 0x00) /* Auto-sleep/wake interrupt disabled */
1745#define FXOS8700_CTRL_REG4_INT_EN_ASLP_EN ((uint8_t) 0x80) /* Auto-sleep/wake interrupt Enabled */
1746#define FXOS8700_CTRL_REG4_INT_EN_FIFO_DIS ((uint8_t) 0x00) /* FIFO interrupt disabled */
1747#define FXOS8700_CTRL_REG4_INT_EN_FIFO_EN ((uint8_t) 0x40) /* FIFO interrupt enabled */
1748#define FXOS8700_CTRL_REG4_INT_EN_TRANS_DIS ((uint8_t) 0x00) /* Transient interrupt disabled */
1749#define FXOS8700_CTRL_REG4_INT_EN_TRANS_EN ((uint8_t) 0x20) /* Transient interrupt enabled */
1750#define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_DIS ((uint8_t) 0x00) /* Orientation (landscape/portrait) interrupt */
1751 /* disabled */
1752#define FXOS8700_CTRL_REG4_INT_EN_LNDPRT_EN ((uint8_t) 0x10) /* Orientation (landscape/portrait) interrupt enabled */
1753#define FXOS8700_CTRL_REG4_INT_EN_PULSE_DIS ((uint8_t) 0x00) /* Pulse detection interrupt disabled */
1754#define FXOS8700_CTRL_REG4_INT_EN_PULSE_EN ((uint8_t) 0x08) /* Pulse detection interrupt enabled */
1755#define FXOS8700_CTRL_REG4_INT_EN_FFMT_DIS ((uint8_t) 0x00) /* Freefall/motion interrupt disabled */
1756#define FXOS8700_CTRL_REG4_INT_EN_FFMT_EN ((uint8_t) 0x04) /* Freefall/motion interrupt enabled */
1757#define FXOS8700_CTRL_REG4_INT_EN_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude interrupt disabled */
1758#define FXOS8700_CTRL_REG4_INT_EN_A_VECM_EN ((uint8_t) 0x02) /* Acceleration vector-magnitude interrupt disabled */
1759#define FXOS8700_CTRL_REG4_INT_EN_DRDY_DIS ((uint8_t) 0x00) /* Data-ready interrupt disabled */
1760#define FXOS8700_CTRL_REG4_INT_EN_DRDY_EN ((uint8_t) 0x01) /* Data-ready interrupt Enabled */
1761/*------------------------------*/
1762
1763
1764
1765/*--------------------------------
1766** Register: CTRL_REG5
1767** Enum: FXOS8700_CTRL_REG5
1768** --
1769** Offset : 0x2E - Interrupt pin (INT1/INT2) map.
1770** ------------------------------*/
1771typedef union {
1772 struct {
1773 uint8_t int_cfg_drdy : 1;
1774 uint8_t int_cfg_a_vecm : 1;
1775 uint8_t int_cfg_ffmt : 1;
1776 uint8_t int_cfg_pulse : 1;
1777 uint8_t int_cfg_lndprt : 1;
1778 uint8_t int_cfg_trans : 1;
1779 uint8_t int_cfg_fifo : 1;
1780 uint8_t int_cfg_aslp : 1;
1781 } b;
1782 uint8_t w;
1783} FXOS8700_CTRL_REG5_t;
1784
1785
1786/*
1787** CTRL_REG5 - Bit field mask definitions
1788*/
1789#define FXOS8700_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01)
1790#define FXOS8700_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0)
1791
1792#define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_MASK ((uint8_t) 0x02)
1793#define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_SHIFT ((uint8_t) 1)
1794
1795#define FXOS8700_CTRL_REG5_INT_CFG_FFMT_MASK ((uint8_t) 0x04)
1796#define FXOS8700_CTRL_REG5_INT_CFG_FFMT_SHIFT ((uint8_t) 2)
1797
1798#define FXOS8700_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08)
1799#define FXOS8700_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3)
1800
1801#define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10)
1802#define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4)
1803
1804#define FXOS8700_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20)
1805#define FXOS8700_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5)
1806
1807#define FXOS8700_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1808#define FXOS8700_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1809
1810#define FXOS8700_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80)
1811#define FXOS8700_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7)
1812
1813
1814/*
1815** CTRL_REG5 - Bit field value definitions
1816*/
1817#define FXOS8700_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1818#define FXOS8700_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin */
1819#define FXOS8700_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1820#define FXOS8700_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin */
1821#define FXOS8700_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1822#define FXOS8700_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin */
1823#define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1824#define FXOS8700_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin */
1825#define FXOS8700_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1826#define FXOS8700_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin */
1827#define FXOS8700_CTRL_REG5_INT_CFG_FFMT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1828#define FXOS8700_CTRL_REG5_INT_CFG_FFMT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin */
1829#define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1830#define FXOS8700_CTRL_REG5_INT_CFG_A_VECM_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 pin */
1831#define FXOS8700_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin */
1832#define FXOS8700_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin */
1833/*------------------------------*/
1834
1835
1836
1837/*--------------------------------
1838** Register: OFF_X
1839** Enum: FXOS8700_OFF_X
1840** --
1841** Offset : 0x2F - X-axis accelerometer offset adjust.
1842** ------------------------------*/
1843typedef uint8_t FXOS8700_OFF_X_t;
1844
1845
1846/*--------------------------------
1847** Register: OFF_Y
1848** Enum: FXOS8700_OFF_Y
1849** --
1850** Offset : 0x30 - Y-axis accelerometer offset adjust.
1851** ------------------------------*/
1852typedef uint8_t FXOS8700_OFF_Y_t;
1853
1854
1855/*--------------------------------
1856** Register: OFF_Z
1857** Enum: FXOS8700_OFF_Z
1858** --
1859** Offset : 0x31 - Z-axis accelerometer offset adjust.
1860** ------------------------------*/
1861typedef uint8_t FXOS8700_OFF_Z_t;
1862
1863
1864
1865/*--------------------------------
1866** Register: M_DR_STATUS
1867** Enum: FXOS8700_M_DR_STATUS
1868** --
1869** Offset : 0x32 - The magnetometer data ready status.
1870** ------------------------------*/
1871typedef union {
1872 struct {
1873 uint8_t xdr : 1;
1874 uint8_t ydr : 1;
1875 uint8_t zdr : 1;
1876 uint8_t zyxdr : 1;
1877 uint8_t xow : 1;
1878 uint8_t yow : 1;
1879 uint8_t zow : 1;
1880 uint8_t zyxow : 1;
1881 } b;
1882 uint8_t w;
1883} FXOS8700_M_DR_STATUS_t;
1884
1885
1886/*
1887** M_DR_STATUS - Bit field mask definitions
1888*/
1889#define FXOS8700_M_DR_STATUS_XDR_MASK ((uint8_t) 0x01)
1890#define FXOS8700_M_DR_STATUS_XDR_SHIFT ((uint8_t) 0)
1891
1892#define FXOS8700_M_DR_STATUS_YDR_MASK ((uint8_t) 0x02)
1893#define FXOS8700_M_DR_STATUS_YDR_SHIFT ((uint8_t) 1)
1894
1895#define FXOS8700_M_DR_STATUS_ZDR_MASK ((uint8_t) 0x04)
1896#define FXOS8700_M_DR_STATUS_ZDR_SHIFT ((uint8_t) 2)
1897
1898#define FXOS8700_M_DR_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
1899#define FXOS8700_M_DR_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
1900
1901#define FXOS8700_M_DR_STATUS_XOW_MASK ((uint8_t) 0x10)
1902#define FXOS8700_M_DR_STATUS_XOW_SHIFT ((uint8_t) 4)
1903
1904#define FXOS8700_M_DR_STATUS_YOW_MASK ((uint8_t) 0x20)
1905#define FXOS8700_M_DR_STATUS_YOW_SHIFT ((uint8_t) 5)
1906
1907#define FXOS8700_M_DR_STATUS_ZOW_MASK ((uint8_t) 0x40)
1908#define FXOS8700_M_DR_STATUS_ZOW_SHIFT ((uint8_t) 6)
1909
1910#define FXOS8700_M_DR_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
1911#define FXOS8700_M_DR_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
1912
1913
1914/*------------------------------*/
1915
1916
1917
1918/*--------------------------------
1919** Register: M_OUT_X_MSB
1920** Enum: FXOS8700_M_OUT_X_MSB
1921** --
1922** Offset : 0x33 - MSB of the 16-bit magnetometer data for X-axis.
1923** ------------------------------*/
1924typedef uint8_t FXOS8700_M_OUT_X_MSB_t;
1925
1926
1927/*--------------------------------
1928** Register: M_OUT_X_LSB
1929** Enum: FXOS8700_M_OUT_X_LSB
1930** --
1931** Offset : 0x34 - LSB of the 16-bit magnetometer data for X-axis.
1932** ------------------------------*/
1933typedef uint8_t FXOS8700_M_OUT_X_LSB_t;
1934
1935
1936/*--------------------------------
1937** Register: M_OUT_Y_MSB
1938** Enum: FXOS8700_M_OUT_Y_MSB
1939** --
1940** Offset : 0x35 - MSB of the 16-bit magnetometer data for Y-axis.
1941** ------------------------------*/
1942typedef uint8_t FXOS8700_M_OUT_Y_MSB_t;
1943
1944
1945/*--------------------------------
1946** Register: M_OUT_Y_LSB
1947** Enum: FXOS8700_M_OUT_Y_LSB
1948** --
1949** Offset : 0x36 - LSB of the 16-bit magnetometer data for Y-axis.
1950** ------------------------------*/
1951typedef uint8_t FXOS8700_M_OUT_Y_LSB_t;
1952
1953
1954/*--------------------------------
1955** Register: M_OUT_Z_MSB
1956** Enum: FXOS8700_M_OUT_Z_MSB
1957** --
1958** Offset : 0x37 - MSB of the 16-bit magnetometer data for Z-axis.
1959** ------------------------------*/
1960typedef uint8_t FXOS8700_M_OUT_Z_MSB_t;
1961
1962
1963/*--------------------------------
1964** Register: M_OUT_Z_LSB
1965** Enum: FXOS8700_M_OUT_Z_LSB
1966** --
1967** Offset : 0x38 - LSB of the 16-bit magnetometer data for Z-axis.
1968** ------------------------------*/
1969typedef uint8_t FXOS8700_M_OUT_Z_LSB_t;
1970
1971
1972
1973/*--------------------------------
1974** Register: CMP_X_MSB
1975** Enum: FXOS8700_CMP_X_MSB
1976** --
1977** Offset : 0x39 - Bits [13:8] of integrated X-axis acceleration data.
1978** ------------------------------*/
1979typedef union {
1980 struct {
1981 uint8_t cmp_x : 6;
1982 } b;
1983 uint8_t w;
1984} FXOS8700_CMP_X_MSB_t;
1985
1986
1987/*
1988** CMP_X_MSB - Bit field mask definitions
1989*/
1990#define FXOS8700_CMP_X_MSB_CMP_X_MASK ((uint8_t) 0x3F)
1991#define FXOS8700_CMP_X_MSB_CMP_X_SHIFT ((uint8_t) 0)
1992
1993
1994/*------------------------------*/
1995
1996
1997
1998/*--------------------------------
1999** Register: CMP_X_LSB
2000** Enum: FXOS8700_CMP_X_LSB
2001** --
2002** Offset : 0x3A - Bits [7:0] of integrated X-axis acceleration data.
2003** ------------------------------*/
2004typedef uint8_t FXOS8700_CMP_X_LSB_t;
2005
2006
2007/*--------------------------------
2008** Register: CMP_Y_MSB
2009** Enum: FXOS8700_CMP_Y_MSB
2010** --
2011** Offset : 0x3B - Bits [13:8] of integrated Y-axis acceleration data.
2012** ------------------------------*/
2013typedef union {
2014 struct {
2015 uint8_t cmp_y : 6;
2016 } b;
2017 uint8_t w;
2018} FXOS8700_CMP_Y_MSB_t;
2019
2020
2021/*
2022** CMP_Y_MSB - Bit field mask definitions
2023*/
2024#define FXOS8700_CMP_Y_MSB_CMP_Y_MASK ((uint8_t) 0x3F)
2025#define FXOS8700_CMP_Y_MSB_CMP_Y_SHIFT ((uint8_t) 0)
2026
2027
2028/*------------------------------*/
2029
2030
2031
2032/*--------------------------------
2033** Register: CMP_Y_LSB
2034** Enum: FXOS8700_CMP_Y_LSB
2035** --
2036** Offset : 0x3C - Bits [7:0] of integrated Y-axis acceleration data.
2037** ------------------------------*/
2038typedef uint8_t FXOS8700_CMP_Y_LSB_t;
2039
2040
2041/*--------------------------------
2042** Register: CMP_Z_MSB
2043** Enum: FXOS8700_CMP_Z_MSB
2044** --
2045** Offset : 0x3D - Bits [13:8] of integrated Z-axis acceleration data.
2046** ------------------------------*/
2047typedef union {
2048 struct {
2049 uint8_t cmp_z : 6;
2050 } b;
2051 uint8_t w;
2052} FXOS8700_CMP_Z_MSB_t;
2053
2054
2055/*
2056** CMP_Z_MSB - Bit field mask definitions
2057*/
2058#define FXOS8700_CMP_Z_MSB_CMP_Z_MASK ((uint8_t) 0x3F)
2059#define FXOS8700_CMP_Z_MSB_CMP_Z_SHIFT ((uint8_t) 0)
2060
2061
2062/*------------------------------*/
2063
2064
2065
2066/*--------------------------------
2067** Register: CMP_Z_LSB
2068** Enum: FXOS8700_CMP_Z_LSB
2069** --
2070** Offset : 0x3E - Bits [7:0] of integrated Z-axis acceleration data.
2071** ------------------------------*/
2072typedef uint8_t FXOS8700_CMP_Z_LSB_t;
2073
2074
2075/*--------------------------------
2076** Register: M_OFF_X_MSB
2077** Enum: FXOS8700_M_OFF_X_MSB
2078** --
2079** Offset : 0x3F - MSB of magnetometer X-axis offset.
2080** ------------------------------*/
2081typedef uint8_t FXOS8700_M_OFF_X_MSB_t;
2082
2083
2084/*--------------------------------
2085** Register: M_OFF_X_LSB
2086** Enum: FXOS8700_M_OFF_X_LSB
2087** --
2088** Offset : 0x40 - LSB of magnetometer X-axis offset.
2089** ------------------------------*/
2090typedef union {
2091 struct {
2092 uint8_t _reserved_ : 1;
2093 uint8_t m_off_x : 7;
2094 } b;
2095 uint8_t w;
2096} FXOS8700_M_OFF_X_LSB_t;
2097
2098
2099/*
2100** M_OFF_X_LSB - Bit field mask definitions
2101*/
2102#define FXOS8700_M_OFF_X_LSB_M_OFF_X_MASK ((uint8_t) 0xFE)
2103#define FXOS8700_M_OFF_X_LSB_M_OFF_X_SHIFT ((uint8_t) 1)
2104
2105
2106/*------------------------------*/
2107
2108
2109
2110/*--------------------------------
2111** Register: M_OFF_Y_MSB
2112** Enum: FXOS8700_M_OFF_Y_MSB
2113** --
2114** Offset : 0x41 - MSB of magnetometer Y-axis offset.
2115** ------------------------------*/
2116typedef uint8_t FXOS8700_M_OFF_Y_MSB_t;
2117
2118
2119/*--------------------------------
2120** Register: M_OFF_Y_LSB
2121** Enum: FXOS8700_M_OFF_Y_LSB
2122** --
2123** Offset : 0x42 - LSB of magnetometer Y-axis offset.
2124** ------------------------------*/
2125typedef union {
2126 struct {
2127 uint8_t _reserved_ : 1;
2128 uint8_t m_off_y : 7;
2129 } b;
2130 uint8_t w;
2131} FXOS8700_M_OFF_Y_LSB_t;
2132
2133
2134/*
2135** M_OFF_Y_LSB - Bit field mask definitions
2136*/
2137#define FXOS8700_M_OFF_Y_LSB_M_OFF_Y_MASK ((uint8_t) 0xFE)
2138#define FXOS8700_M_OFF_Y_LSB_M_OFF_Y_SHIFT ((uint8_t) 1)
2139
2140
2141/*------------------------------*/
2142
2143
2144
2145/*--------------------------------
2146** Register: M_OFF_Z_MSB
2147** Enum: FXOS8700_M_OFF_Z_MSB
2148** --
2149** Offset : 0x43 - MSB of magnetometer Z-axis offset.
2150** ------------------------------*/
2151typedef uint8_t FXOS8700_M_OFF_Z_MSB_t;
2152
2153
2154/*--------------------------------
2155** Register: M_OFF_Z_LSB
2156** Enum: FXOS8700_M_OFF_Z_LSB
2157** --
2158** Offset : 0x44 - LSB of magnetometer Z-axis offset.
2159** ------------------------------*/
2160typedef union {
2161 struct {
2162 uint8_t _reserved_ : 1;
2163 uint8_t m_off_z : 7;
2164 } b;
2165 uint8_t w;
2166} FXOS8700_M_OFF_Z_LSB_t;
2167
2168
2169/*
2170** M_OFF_Z_LSB - Bit field mask definitions
2171*/
2172#define FXOS8700_M_OFF_Z_LSB_M_OFF_Z_MASK ((uint8_t) 0xFE)
2173#define FXOS8700_M_OFF_Z_LSB_M_OFF_Z_SHIFT ((uint8_t) 1)
2174
2175
2176/*------------------------------*/
2177
2178
2179
2180/*--------------------------------
2181** Register: MAX_X_MSB
2182** Enum: FXOS8700_MAX_X_MSB
2183** --
2184** Offset : 0x45 - Magnetometer X-axis maximum value MSB.
2185** ------------------------------*/
2186typedef uint8_t FXOS8700_MAX_X_MSB_t;
2187
2188
2189/*--------------------------------
2190** Register: MAX_X_LSB
2191** Enum: FXOS8700_MAX_X_LSB
2192** --
2193** Offset : 0x46 - Magnetometer X-axis maximum value LSB.
2194** ------------------------------*/
2195typedef uint8_t FXOS8700_MAX_X_LSB_t;
2196
2197
2198/*--------------------------------
2199** Register: MAX_Y_MSB
2200** Enum: FXOS8700_MAX_Y_MSB
2201** --
2202** Offset : 0x47 - Magnetometer Y-axis maximum value MSB.
2203** ------------------------------*/
2204typedef uint8_t FXOS8700_MAX_Y_MSB_t;
2205
2206
2207/*--------------------------------
2208** Register: MAX_Y_LSB
2209** Enum: FXOS8700_MAX_Y_LSB
2210** --
2211** Offset : 0x48 - Magnetometer Y-axis maximum value LSB.
2212** ------------------------------*/
2213typedef uint8_t FXOS8700_MAX_Y_LSB_t;
2214
2215
2216/*--------------------------------
2217** Register: MAX_Z_MSB
2218** Enum: FXOS8700_MAX_Z_MSB
2219** --
2220** Offset : 0x49 - Magnetometer Z-axis maximum value MSB.
2221** ------------------------------*/
2222typedef uint8_t FXOS8700_MAX_Z_MSB_t;
2223
2224
2225/*--------------------------------
2226** Register: MAX_Z_LSB
2227** Enum: FXOS8700_MAX_Z_LSB
2228** --
2229** Offset : 0x4A - Magnetometer Z-axis maximum value LSB.
2230** ------------------------------*/
2231typedef uint8_t FXOS8700_MAX_Z_LSB_t;
2232
2233
2234/*--------------------------------
2235** Register: MIN_X_MSB
2236** Enum: FXOS8700_MIN_X_MSB
2237** --
2238** Offset : 0x4B - Magnetometer X-axis minimum value MSB.
2239** ------------------------------*/
2240typedef uint8_t FXOS8700_MIN_X_MSB_t;
2241
2242
2243/*--------------------------------
2244** Register: MIN_X_LSB
2245** Enum: FXOS8700_MIN_X_LSB
2246** --
2247** Offset : 0x4C - Magnetometer X-axis minimum value LSB.
2248** ------------------------------*/
2249typedef uint8_t FXOS8700_MIN_X_LSB_t;
2250
2251
2252/*--------------------------------
2253** Register: MIN_Y_MSB
2254** Enum: FXOS8700_MIN_Y_MSB
2255** --
2256** Offset : 0x4D - Magnetometer Y-axis minimum value MSB.
2257** ------------------------------*/
2258typedef uint8_t FXOS8700_MIN_Y_MSB_t;
2259
2260
2261/*--------------------------------
2262** Register: MIN_Y_LSB
2263** Enum: FXOS8700_MIN_Y_LSB
2264** --
2265** Offset : 0x4E - Magnetometer Y-axis minimum value LSB.
2266** ------------------------------*/
2267typedef uint8_t FXOS8700_MIN_Y_LSB_t;
2268
2269
2270/*--------------------------------
2271** Register: MIN_Z_MSB
2272** Enum: FXOS8700_MIN_Z_MSB
2273** --
2274** Offset : 0x4F - Magnetometer Z-axis minimum value MSB.
2275** ------------------------------*/
2276typedef uint8_t FXOS8700_MIN_Z_MSB_t;
2277
2278
2279/*--------------------------------
2280** Register: MIN_Z_LSB
2281** Enum: FXOS8700_MIN_Z_LSB
2282** --
2283** Offset : 0x50 - Magnetometer Z-axis minimum value LSB.
2284** ------------------------------*/
2285typedef uint8_t FXOS8700_MIN_Z_LSB_t;
2286
2287
2288
2289/*--------------------------------
2290** Register: TEMP
2291** Enum: FXOS8700_TEMP
2292** --
2293** Offset : 0x51 - Device temperature with a valid range of -128 to 127 degrees C.
2294** ------------------------------*/
2295typedef union {
2296 struct {
2297 uint8_t die_temperature;
2298 } b;
2299 uint8_t w;
2300} FXOS8700_TEMP_t;
2301
2302
2303/*
2304** TEMP - Bit field mask definitions
2305*/
2306#define FXOS8700_TEMP_DIE_TEMPERATURE_MASK ((uint8_t) 0xFF)
2307#define FXOS8700_TEMP_DIE_TEMPERATURE_SHIFT ((uint8_t) 0)
2308
2309
2310/*------------------------------*/
2311
2312
2313
2314/*--------------------------------
2315** Register: M_THS_CFG
2316** Enum: FXOS8700_M_THS_CFG
2317** --
2318** Offset : 0x52 - Magnetic threshold detection function configuration.
2319** ------------------------------*/
2320typedef union {
2321 struct {
2322 uint8_t m_ths_int_cfg : 1;
2323 uint8_t m_ths_int_en : 1;
2324 uint8_t m_ths_wake_en : 1;
2325 uint8_t m_ths_xefe : 1;
2326 uint8_t m_ths_yefe : 1;
2327 uint8_t m_ths_zefe : 1;
2328 uint8_t m_ths_oae : 1;
2329 uint8_t m_ths_ele : 1;
2330 } b;
2331 uint8_t w;
2332} FXOS8700_M_THS_CFG_t;
2333
2334
2335/*
2336** M_THS_CFG - Bit field mask definitions
2337*/
2338#define FXOS8700_M_THS_CFG_M_THS_INT_CFG_MASK ((uint8_t) 0x01)
2339#define FXOS8700_M_THS_CFG_M_THS_INT_CFG_SHIFT ((uint8_t) 0)
2340
2341#define FXOS8700_M_THS_CFG_M_THS_INT_EN_MASK ((uint8_t) 0x02)
2342#define FXOS8700_M_THS_CFG_M_THS_INT_EN_SHIFT ((uint8_t) 1)
2343
2344#define FXOS8700_M_THS_CFG_M_THS_WAKE_EN_MASK ((uint8_t) 0x04)
2345#define FXOS8700_M_THS_CFG_M_THS_WAKE_EN_SHIFT ((uint8_t) 2)
2346
2347#define FXOS8700_M_THS_CFG_M_THS_XEFE_MASK ((uint8_t) 0x08)
2348#define FXOS8700_M_THS_CFG_M_THS_XEFE_SHIFT ((uint8_t) 3)
2349
2350#define FXOS8700_M_THS_CFG_M_THS_YEFE_MASK ((uint8_t) 0x10)
2351#define FXOS8700_M_THS_CFG_M_THS_YEFE_SHIFT ((uint8_t) 4)
2352
2353#define FXOS8700_M_THS_CFG_M_THS_ZEFE_MASK ((uint8_t) 0x20)
2354#define FXOS8700_M_THS_CFG_M_THS_ZEFE_SHIFT ((uint8_t) 5)
2355
2356#define FXOS8700_M_THS_CFG_M_THS_OAE_MASK ((uint8_t) 0x40)
2357#define FXOS8700_M_THS_CFG_M_THS_OAE_SHIFT ((uint8_t) 6)
2358
2359#define FXOS8700_M_THS_CFG_M_THS_ELE_MASK ((uint8_t) 0x80)
2360#define FXOS8700_M_THS_CFG_M_THS_ELE_SHIFT ((uint8_t) 7)
2361
2362
2363/*------------------------------*/
2364
2365
2366
2367/*--------------------------------
2368** Register: M_THS_SRC
2369** Enum: FXOS8700_M_THS_SRC
2370** --
2371** Offset : 0x53 - Magnetic threshold event source register.
2372** ------------------------------*/
2373typedef union {
2374 struct {
2375 uint8_t m_ths_xhp : 1;
2376 uint8_t m_ths_xhe : 1;
2377 uint8_t m_ths_yhp : 1;
2378 uint8_t m_ths_yhe : 1;
2379 uint8_t m_ths_zhp : 1;
2380 uint8_t m_ths_zhe : 1;
2381 uint8_t _reserved_ : 1;
2382 uint8_t m_ths_ea : 1;
2383 } b;
2384 uint8_t w;
2385} FXOS8700_M_THS_SRC_t;
2386
2387
2388/*
2389** M_THS_SRC - Bit field mask definitions
2390*/
2391#define FXOS8700_M_THS_SRC_M_THS_XHP_MASK ((uint8_t) 0x01)
2392#define FXOS8700_M_THS_SRC_M_THS_XHP_SHIFT ((uint8_t) 0)
2393
2394#define FXOS8700_M_THS_SRC_M_THS_XHE_MASK ((uint8_t) 0x02)
2395#define FXOS8700_M_THS_SRC_M_THS_XHE_SHIFT ((uint8_t) 1)
2396
2397#define FXOS8700_M_THS_SRC_M_THS_YHP_MASK ((uint8_t) 0x04)
2398#define FXOS8700_M_THS_SRC_M_THS_YHP_SHIFT ((uint8_t) 2)
2399
2400#define FXOS8700_M_THS_SRC_M_THS_YHE_MASK ((uint8_t) 0x08)
2401#define FXOS8700_M_THS_SRC_M_THS_YHE_SHIFT ((uint8_t) 3)
2402
2403#define FXOS8700_M_THS_SRC_M_THS_ZHP_MASK ((uint8_t) 0x10)
2404#define FXOS8700_M_THS_SRC_M_THS_ZHP_SHIFT ((uint8_t) 4)
2405
2406#define FXOS8700_M_THS_SRC_M_THS_ZHE_MASK ((uint8_t) 0x20)
2407#define FXOS8700_M_THS_SRC_M_THS_ZHE_SHIFT ((uint8_t) 5)
2408
2409#define FXOS8700_M_THS_SRC_M_THS_EA_MASK ((uint8_t) 0x80)
2410#define FXOS8700_M_THS_SRC_M_THS_EA_SHIFT ((uint8_t) 7)
2411
2412
2413/*------------------------------*/
2414
2415
2416
2417/*--------------------------------
2418** Register: M_THS_X_MSB
2419** Enum: FXOS8700_M_THS_X_MSB
2420** --
2421** Offset : 0x54 - X-axis magnetic threshold MSB.
2422** ------------------------------*/
2423typedef union {
2424 struct {
2425 uint8_t m_ths_x : 7;
2426 } b;
2427 uint8_t w;
2428} FXOS8700_M_THS_X_MSB_t;
2429
2430
2431/*
2432** M_THS_X_MSB - Bit field mask definitions
2433*/
2434#define FXOS8700_M_THS_X_MSB_M_THS_X_MASK ((uint8_t) 0x7F)
2435#define FXOS8700_M_THS_X_MSB_M_THS_X_SHIFT ((uint8_t) 0)
2436
2437
2438/*------------------------------*/
2439
2440
2441
2442/*--------------------------------
2443** Register: M_THS_X_LSB
2444** Enum: FXOS8700_M_THS_X_LSB
2445** --
2446** Offset : 0x55 - X-axis magnetic threshold LSB.
2447** ------------------------------*/
2448typedef uint8_t FXOS8700_M_THS_X_LSB_t;
2449
2450
2451/*--------------------------------
2452** Register: M_THS_Y_MSB
2453** Enum: FXOS8700_M_THS_Y_MSB
2454** --
2455** Offset : 0x56 - Y-axis magnetic threshold MSB.
2456** ------------------------------*/
2457typedef union {
2458 struct {
2459 uint8_t m_ths_y : 7;
2460 } b;
2461 uint8_t w;
2462} FXOS8700_M_THS_Y_MSB_t;
2463
2464
2465/*
2466** M_THS_Y_MSB - Bit field mask definitions
2467*/
2468#define FXOS8700_M_THS_Y_MSB_M_THS_Y_MASK ((uint8_t) 0x7F)
2469#define FXOS8700_M_THS_Y_MSB_M_THS_Y_SHIFT ((uint8_t) 0)
2470
2471
2472/*------------------------------*/
2473
2474
2475
2476/*--------------------------------
2477** Register: M_THS_Y_LSB
2478** Enum: FXOS8700_M_THS_Y_LSB
2479** --
2480** Offset : 0x57 - Y-axis magnetic threshold LSB.
2481** ------------------------------*/
2482typedef uint8_t FXOS8700_M_THS_Y_LSB_t;
2483
2484
2485/*--------------------------------
2486** Register: M_THS_Z_MSB
2487** Enum: FXOS8700_M_THS_Z_MSB
2488** --
2489** Offset : 0x58 - Z-axis magnetic threshold MSB.
2490** ------------------------------*/
2491typedef union {
2492 struct {
2493 uint8_t m_ths_z : 7;
2494 } b;
2495 uint8_t w;
2496} FXOS8700_M_THS_Z_MSB_t;
2497
2498
2499/*
2500** M_THS_Z_MSB - Bit field mask definitions
2501*/
2502#define FXOS8700_M_THS_Z_MSB_M_THS_Z_MASK ((uint8_t) 0x7F)
2503#define FXOS8700_M_THS_Z_MSB_M_THS_Z_SHIFT ((uint8_t) 0)
2504
2505
2506/*------------------------------*/
2507
2508
2509
2510/*--------------------------------
2511** Register: M_THS_Z_LSB
2512** Enum: FXOS8700_M_THS_Z_LSB
2513** --
2514** Offset : 0x59 - Z-axis magnetic threshold LSB.
2515** ------------------------------*/
2516typedef uint8_t FXOS8700_M_THS_Z_LSB_t;
2517
2518
2519/*--------------------------------
2520** Register: M_THS_COUNT
2521** Enum: FXOS8700_M_THS_COUNT
2522** --
2523** Offset : 0x5A - Magnetic threshold debounce counter.
2524** ------------------------------*/
2525typedef uint8_t FXOS8700_M_THS_COUNT_t;
2526
2527
2528
2529/*--------------------------------
2530** Register: M_CTRL_REG1
2531** Enum: FXOS8700_M_CTRL_REG1
2532** --
2533** Offset : 0x5B - Control for magnetometer sensor functions.
2534** ------------------------------*/
2535typedef union {
2536 struct {
2537 uint8_t m_hms : 2;
2538 uint8_t m_os : 3; /* M-cell oversample ratio */
2539
2540 uint8_t m_ost : 1; /* One-shot triggered magnetic measurement mode: */
2541
2542 uint8_t m_rst : 1;
2543 uint8_t m_acal : 1;
2544 } b;
2545 uint8_t w;
2546} FXOS8700_M_CTRL_REG1_t;
2547
2548
2549/*
2550** M_CTRL_REG1 - Bit field mask definitions
2551*/
2552#define FXOS8700_M_CTRL_REG1_M_HMS_MASK ((uint8_t) 0x03)
2553#define FXOS8700_M_CTRL_REG1_M_HMS_SHIFT ((uint8_t) 0)
2554
2555#define FXOS8700_M_CTRL_REG1_M_OS_MASK ((uint8_t) 0x1C)
2556#define FXOS8700_M_CTRL_REG1_M_OS_SHIFT ((uint8_t) 2)
2557
2558#define FXOS8700_M_CTRL_REG1_M_OST_MASK ((uint8_t) 0x20)
2559#define FXOS8700_M_CTRL_REG1_M_OST_SHIFT ((uint8_t) 5)
2560
2561#define FXOS8700_M_CTRL_REG1_M_RST_MASK ((uint8_t) 0x40)
2562#define FXOS8700_M_CTRL_REG1_M_RST_SHIFT ((uint8_t) 6)
2563
2564#define FXOS8700_M_CTRL_REG1_M_ACAL_MASK ((uint8_t) 0x80)
2565#define FXOS8700_M_CTRL_REG1_M_ACAL_SHIFT ((uint8_t) 7)
2566
2567
2568/*
2569** M_CTRL_REG1 - Bit field value definitions
2570*/
2571#define FXOS8700_M_CTRL_REG1_M_ACAL_EN ((uint8_t) 0x80) /* Auto-calibration feature enabled */
2572#define FXOS8700_M_CTRL_REG1_M_ACAL_DISABLE ((uint8_t) 0x00) /* Auto-calibration feature disabled */
2573#define FXOS8700_M_CTRL_REG1_M_RST_EN ((uint8_t) 0x40) /* One-shot magnetic sensor reset enabled, hw */
2574 /* cleared when complete */
2575#define FXOS8700_M_CTRL_REG1_M_RST_DISABLE ((uint8_t) 0x00) /* No magnetic sensor reset active */
2576#define FXOS8700_M_CTRL_REG1_M_OST_EN ((uint8_t) 0x20) /* If device is in Active mode no action is taken. */
2577 /* If device is in Standby mode, take one set of */
2578 /* magnetic measurements, clear this bit, and */
2579 /* return to Standby mode. */
2580#define FXOS8700_M_CTRL_REG1_M_OST_DISABLE ((uint8_t) 0x00) /* No action taken, or one-shot measurement */
2581 /* complete */
2582#define FXOS8700_M_CTRL_REG1_M_OS_OSR0 ((uint8_t) 0x00) /* 1.56=16, 6.25=4, 12.5=2, 50=2, 100=2, 200=2, */
2583 /* 400=2, 800=2 */
2584#define FXOS8700_M_CTRL_REG1_M_OS_OSR1 ((uint8_t) 0x04) /* 1.56=16, 6.25=4, 12.5=2, 50=2, 100=2, 200=2, */
2585 /* 400=2, 800=2 */
2586#define FXOS8700_M_CTRL_REG1_M_OS_OSR2 ((uint8_t) 0x08) /* 1.56=32, 6.25=8, 12.5=4, 50=2, 100=2, 200=2, */
2587 /* 400=2, 800=2 */
2588#define FXOS8700_M_CTRL_REG1_M_OS_OSR3 ((uint8_t) 0x0c) /* 1.56=64, 6.25=16, 12.5=8, 50=2, 100=2, 200=2, */
2589 /* 400=2, 800=2 */
2590#define FXOS8700_M_CTRL_REG1_M_OS_OSR4 ((uint8_t) 0x10) /* 1.56=128, 6.25=32, 12.5=16, 50=4, 100=2, 200=2, */
2591 /* 400=2, 800=2 */
2592#define FXOS8700_M_CTRL_REG1_M_OS_OSR5 ((uint8_t) 0x14) /* 1.56=256, 6.25=64, 12.5=32, 50=8, 100=4, 200=2, */
2593 /* 400=2, 800=2 */
2594#define FXOS8700_M_CTRL_REG1_M_OS_OSR6 ((uint8_t) 0x18) /* 1.56=512, 6.25=128, 12.5=64, 50=16, 100=8, */
2595 /* 200=4, 400=2, 800=2 */
2596#define FXOS8700_M_CTRL_REG1_M_OS_OSR7 ((uint8_t) 0x1c) /* 1.56=1024, 6.25=256, 12.5=128, 50=32, 100=16, */
2597 /* 200=8, 400=4, 800=2 */
2598#define FXOS8700_M_CTRL_REG1_M_HMS_ACCEL_ONLY ((uint8_t) 0x00) /* 0b00 = Only accelerometer sensor is active */
2599#define FXOS8700_M_CTRL_REG1_M_HMS_MAG_ONLY ((uint8_t) 0x01) /* 0b01 = Only magnetometer sensor is active */
2600#define FXOS8700_M_CTRL_REG1_M_HMS_HYBRID_MODE ((uint8_t) 0x03) /* 0b11 = Hybrid mode, both accelerometer and */
2601 /* magnetometer sensors are active */
2602/*------------------------------*/
2603
2604
2605
2606/*--------------------------------
2607** Register: M_CTRL_REG2
2608** Enum: FXOS8700_M_CTRL_REG2
2609** --
2610** Offset : 0x5C - Control for magnetometer sensor functions.
2611** ------------------------------*/
2612typedef union {
2613 struct {
2614 uint8_t m_rst_cnt : 2;
2615 uint8_t m_maxmin_rst : 1;
2616 uint8_t m_maxmin_dis_ths : 1;
2617 uint8_t m_maxmin_dis : 1;
2618 uint8_t m_autoinc : 1;
2619 } b;
2620 uint8_t w;
2621} FXOS8700_M_CTRL_REG2_t;
2622
2623
2624/*
2625** M_CTRL_REG2 - Bit field mask definitions
2626*/
2627#define FXOS8700_M_CTRL_REG2_M_RST_CNT_MASK ((uint8_t) 0x03)
2628#define FXOS8700_M_CTRL_REG2_M_RST_CNT_SHIFT ((uint8_t) 0)
2629
2630#define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_MASK ((uint8_t) 0x04)
2631#define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_SHIFT ((uint8_t) 2)
2632
2633#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_MASK ((uint8_t) 0x08)
2634#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_SHIFT ((uint8_t) 3)
2635
2636#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_MASK ((uint8_t) 0x10)
2637#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_SHIFT ((uint8_t) 4)
2638
2639#define FXOS8700_M_CTRL_REG2_M_AUTOINC_MASK ((uint8_t) 0x20)
2640#define FXOS8700_M_CTRL_REG2_M_AUTOINC_SHIFT ((uint8_t) 5)
2641
2642
2643/*
2644** M_CTRL_REG2 - Bit field value definitions
2645*/
2646#define FXOS8700_M_CTRL_REG2_M_AUTOINC_HYBRID_MODE ((uint8_t) 0x20) /* With hyb_autoinc_mode = 1 and fast-read mode is */
2647 /* disabled (CTRL_REG1 [f_read] = 0), the register */
2648 /* address will automatically advance to register */
2649 /* x33 (M_OUT_X_MSB) after reading register x06 */
2650 /* (OUT_Z_LSB) in burst-read mode. */
2651 /* For hyb_autoinc_mode = 1 and fast read mode */
2652 /* enabled (CTRL_REG1[f_read = 1) the register */
2653 /* address will automatically advance to register */
2654 /* x33 (M_OUT_X_MSB) after reading register x05 */
2655 /* (OUT_Z_MSB) during a burstread mode. Please */
2656 /* refer to the register map auto-increment address */
2657 /* column for further information. */
2658#define FXOS8700_M_CTRL_REG2_M_AUTOINC_ACCEL_ONLY_MODE ((uint8_t) 0x00) /* hyb_autoinc_mode = 0 */
2659#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_DIS ((uint8_t) 0x00) /* Magnetic min/max detection function is enabled */
2660#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_EN ((uint8_t) 0x10) /* Magnetic min/max detection function is disabled */
2661#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_DIS ((uint8_t) 0x00) /* No impact to magnetic min/max detection function */
2662 /* on a magnetic threshold event */
2663#define FXOS8700_M_CTRL_REG2_M_MAXMIN_DIS_THS_EN ((uint8_t) 0x08) /* Magnetic min/max detection function is disabled */
2664 /* when magnetic threshold event is triggered */
2665#define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_NO_SEQUENCE ((uint8_t) 0x00) /* No reset sequence is active */
2666#define FXOS8700_M_CTRL_REG2_M_MAXMIN_RST_SET ((uint8_t) 0x04) /* Setting this bit resets the MIN_X/Y/Z and */
2667 /* MAX_X/Y/Z registers to 0x7FFF and 0x8000 */
2668#define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY1 ((uint8_t) 0x00) /* Automatic magnetic reset at the beginning of */
2669 /* each ODR cycle (default). */
2670#define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY16 ((uint8_t) 0x01) /* Automatic magnetic reset every 16 ODR cycles */
2671#define FXOS8700_M_CTRL_REG2_M_RST_CNT_EVERY512 ((uint8_t) 0x02) /* Automatic magnetic reset every 512 ODR cycles */
2672#define FXOS8700_M_CTRL_REG2_M_RST_CNT_DISABLE ((uint8_t) 0x03) /* Automatic magnetic reset is disabled. Magnetic */
2673 /* reset only occurs automatically on a transition */
2674 /* from Standby to Active mode, or can be triggered */
2675 /* manually by setting M_CTRL_REG1[m_rst] = 1 */
2676/*------------------------------*/
2677
2678
2679
2680
2681/*--------------------------------
2682** Register: M_CTRL_REG3
2683** Enum: FXOS8700_M_CTRL_REG3
2684** --
2685** Offset : 0x5D - Control for magnetometer sensor functions.
2686** ------------------------------*/
2687typedef union {
2688 struct {
2689 uint8_t m_st_xy : 2;
2690 uint8_t m_st_z : 1;
2691 uint8_t m_ths_xyz_update : 1;
2692 uint8_t m_aslp_os : 3;
2693 uint8_t m_raw : 1;
2694 } b;
2695 uint8_t w;
2696} FXOS8700_M_CTRL_REG3_t;
2697
2698
2699/*
2700** M_CTRL_REG3 - Bit field mask definitions
2701*/
2702#define FXOS8700_M_CTRL_REG3_M_ST_XY_MASK ((uint8_t) 0x03)
2703#define FXOS8700_M_CTRL_REG3_M_ST_XY_SHIFT ((uint8_t) 0)
2704
2705#define FXOS8700_M_CTRL_REG3_M_ST_Z_MASK ((uint8_t) 0x04)
2706#define FXOS8700_M_CTRL_REG3_M_ST_Z_SHIFT ((uint8_t) 2)
2707
2708#define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_MASK ((uint8_t) 0x08)
2709#define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_SHIFT ((uint8_t) 3)
2710
2711#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_MASK ((uint8_t) 0x70)
2712#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_SHIFT ((uint8_t) 4)
2713
2714#define FXOS8700_M_CTRL_REG3_M_RAW_MASK ((uint8_t) 0x80)
2715#define FXOS8700_M_CTRL_REG3_M_RAW_SHIFT ((uint8_t) 7)
2716
2717
2718/*
2719** M_CTRL_REG3 - Bit field value definitions
2720*/
2721#define FXOS8700_M_CTRL_REG3_M_RAW_EN ((uint8_t) 0x80) /* Values stored in the M_OFF_X/Y/Z registers are */
2722 /* applied to the magnetic sample data */
2723#define FXOS8700_M_CTRL_REG3_M_RAW_DIS ((uint8_t) 0x00) /* Values stored in M_OFF_X/Y/Z are not applied to */
2724 /* the magnetic sample data */
2725#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_0 ((uint8_t) 0x00) /* OSR 0 look at table 203 */
2726#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_1 ((uint8_t) 0x10) /* OSR 1 look at table 203 */
2727#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_2 ((uint8_t) 0x20) /* OSR 2 look at table 203 */
2728#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_3 ((uint8_t) 0x30) /* OSR 3 look at table 203 */
2729#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_4 ((uint8_t) 0x40) /* OSR 4 look at table 203 */
2730#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_5 ((uint8_t) 0x50) /* OSR 5 look at table 203 */
2731#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_6 ((uint8_t) 0x60) /* OSR 6 look at table 203 */
2732#define FXOS8700_M_CTRL_REG3_M_ASLP_OS_OSR_7 ((uint8_t) 0x70) /* OSR look at table 203 */
2733#define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_EN ((uint8_t) 0x08) /* Only the reference value for the axis that */
2734 /* triggered the detection event is updated */
2735#define FXOS8700_M_CTRL_REG3_M_THS_XYZ_UPDATE_DIS ((uint8_t) 0x00) /* X, Y and Z reference values are all updated when */
2736 /* the function triggers on any of the X, Y, or Z */
2737 /* axes */
2738/*------------------------------*/
2739
2740
2741
2742/*--------------------------------
2743** Register: M_INT_SRC
2744** Enum: FXOS8700_M_INT_SRC
2745** --
2746** Offset : 0x5E - Magnetometer interrupt source.
2747** ------------------------------*/
2748typedef union {
2749 struct {
2750 uint8_t src_m_drdy : 1;
2751 uint8_t src_m_vecm : 1;
2752 uint8_t src_m_ths : 1;
2753 } b;
2754 uint8_t w;
2755} FXOS8700_M_INT_SRC_t;
2756
2757
2758/*
2759** M_INT_SRC - Bit field mask definitions
2760*/
2761#define FXOS8700_M_INT_SRC_SRC_M_DRDY_MASK ((uint8_t) 0x01)
2762#define FXOS8700_M_INT_SRC_SRC_M_DRDY_SHIFT ((uint8_t) 0)
2763
2764#define FXOS8700_M_INT_SRC_SRC_M_VECM_MASK ((uint8_t) 0x02)
2765#define FXOS8700_M_INT_SRC_SRC_M_VECM_SHIFT ((uint8_t) 1)
2766
2767#define FXOS8700_M_INT_SRC_SRC_M_THS_MASK ((uint8_t) 0x04)
2768#define FXOS8700_M_INT_SRC_SRC_M_THS_SHIFT ((uint8_t) 2)
2769
2770
2771/*------------------------------*/
2772
2773
2774
2775/*--------------------------------
2776** Register: A_VECM_CFG
2777** Enum: FXOS8700_A_VECM_CFG
2778** --
2779** Offset : 0x5F - Acceleration vector magnitude configuration register.
2780** ------------------------------*/
2781typedef union {
2782 struct {
2783 uint8_t _reserved_ : 4;
2784 uint8_t a_vecm_updm : 1;
2785 uint8_t a_vecm_initm : 1;
2786 uint8_t a_vecm_ele : 1;
2787 uint8_t a_vecm_en : 1;
2788 } b;
2789 uint8_t w;
2790} FXOS8700_A_VECM_CFG_t;
2791
2792
2793/*
2794** A_VECM_CFG - Bit field mask definitions
2795*/
2796#define FXOS8700_A_VECM_CFG_A_VECM_UPDM_MASK ((uint8_t) 0x10)
2797#define FXOS8700_A_VECM_CFG_A_VECM_UPDM_SHIFT ((uint8_t) 4)
2798
2799#define FXOS8700_A_VECM_CFG_A_VECM_INITM_MASK ((uint8_t) 0x20)
2800#define FXOS8700_A_VECM_CFG_A_VECM_INITM_SHIFT ((uint8_t) 5)
2801
2802#define FXOS8700_A_VECM_CFG_A_VECM_ELE_MASK ((uint8_t) 0x40)
2803#define FXOS8700_A_VECM_CFG_A_VECM_ELE_SHIFT ((uint8_t) 6)
2804
2805#define FXOS8700_A_VECM_CFG_A_VECM_EN_MASK ((uint8_t) 0x80)
2806#define FXOS8700_A_VECM_CFG_A_VECM_EN_SHIFT ((uint8_t) 7)
2807
2808
2809/*------------------------------*/
2810
2811
2812
2813/*--------------------------------
2814** Register: A_VECM_THS_MSB
2815** Enum: FXOS8700_A_VECM_THS_MSB
2816** --
2817** Offset : 0x60 - Acceleration vector magnitude threshold MSB.
2818** ------------------------------*/
2819typedef union {
2820 struct {
2821 uint8_t a_vbecm_ths : 5;
2822 uint8_t _reserved_ : 2;
2823 uint8_t a_vbecm_dbcntm : 1;
2824 } b;
2825 uint8_t w;
2826} FXOS8700_A_VECM_THS_MSB_t;
2827
2828
2829/*
2830** A_VECM_THS_MSB - Bit field mask definitions
2831*/
2832#define FXOS8700_A_VECM_THS_MSB_A_VBECM_THS_MASK ((uint8_t) 0x1F)
2833#define FXOS8700_A_VECM_THS_MSB_A_VBECM_THS_SHIFT ((uint8_t) 0)
2834
2835#define FXOS8700_A_VECM_THS_MSB_A_VBECM_DBCNTM_MASK ((uint8_t) 0x80)
2836#define FXOS8700_A_VECM_THS_MSB_A_VBECM_DBCNTM_SHIFT ((uint8_t) 7)
2837
2838
2839/*------------------------------*/
2840
2841
2842
2843/*--------------------------------
2844** Register: A_VECM_THS_LSB
2845** Enum: FXOS8700_A_VECM_THS_LSB
2846** --
2847** Offset : 0x61 - Acceleration vector magnitude threshold LSB.
2848** ------------------------------*/
2849typedef uint8_t FXOS8700_A_VECM_THS_LSB_t;
2850
2851
2852/*--------------------------------
2853** Register: A_VECM_CNT
2854** Enum: FXOS8700_A_VECM_CNT
2855** --
2856** Offset : 0x62 - Acceleration vector magnitude debounce count.
2857** ------------------------------*/
2858typedef uint8_t FXOS8700_A_VECM_CNT_t;
2859
2860
2861
2862/*--------------------------------
2863** Register: A_VECM_INITX_MSB
2864** Enum: FXOS8700_A_VECM_INITX_MSB
2865** --
2866** Offset : 0x63 - Acceleration vector magnitude X-axis reference value MSB.
2867** ------------------------------*/
2868typedef union {
2869 struct {
2870 uint8_t a_vecm_initx : 6;
2871 } b;
2872 uint8_t w;
2873} FXOS8700_A_VECM_INITX_MSB_t;
2874
2875
2876/*
2877** A_VECM_INITX_MSB - Bit field mask definitions
2878*/
2879#define FXOS8700_A_VECM_INITX_MSB_A_VECM_INITX_MASK ((uint8_t) 0x3F)
2880#define FXOS8700_A_VECM_INITX_MSB_A_VECM_INITX_SHIFT ((uint8_t) 0)
2881
2882
2883/*------------------------------*/
2884
2885
2886
2887/*--------------------------------
2888** Register: A_VECM_INITX_LSB
2889** Enum: FXOS8700_A_VECM_INITX_LSB
2890** --
2891** Offset : 0x64 - Acceleration vector magnitude X-axis reference value LSB.
2892** ------------------------------*/
2893typedef uint8_t FXOS8700_A_VECM_INITX_LSB_t;
2894
2895
2896/*--------------------------------
2897** Register: A_VECM_INITY_MSB
2898** Enum: FXOS8700_A_VECM_INITY_MSB
2899** --
2900** Offset : 0x65 - Acceleration vector magnitude Y-axis reference value MSB.
2901** ------------------------------*/
2902typedef union {
2903 struct {
2904 uint8_t a_vecm_inity : 6;
2905 } b;
2906 uint8_t w;
2907} FXOS8700_A_VECM_INITY_MSB_t;
2908
2909
2910/*
2911** A_VECM_INITY_MSB - Bit field mask definitions
2912*/
2913#define FXOS8700_A_VECM_INITY_MSB_A_VECM_INITY_MASK ((uint8_t) 0x3F)
2914#define FXOS8700_A_VECM_INITY_MSB_A_VECM_INITY_SHIFT ((uint8_t) 0)
2915
2916
2917/*------------------------------*/
2918
2919
2920
2921/*--------------------------------
2922** Register: A_VECM_INITY_LSB
2923** Enum: FXOS8700_A_VECM_INITY_LSB
2924** --
2925** Offset : 0x66 - Acceleration vector magnitude Y-axis reference value LSB.
2926** ------------------------------*/
2927typedef uint8_t FXOS8700_A_VECM_INITY_LSB_t;
2928
2929
2930/*--------------------------------
2931** Register: A_VECM_INITZ_MSB
2932** Enum: FXOS8700_A_VECM_INITZ_MSB
2933** --
2934** Offset : 0x67 - Acceleration vector magnitude Z-axis reference value MSB.
2935** ------------------------------*/
2936typedef union {
2937 struct {
2938 uint8_t a_vecm_initz : 6;
2939 } b;
2940 uint8_t w;
2941} FXOS8700_A_VECM_INITZ_MSB_t;
2942
2943
2944/*
2945** A_VECM_INITZ_MSB - Bit field mask definitions
2946*/
2947#define FXOS8700_A_VECM_INITZ_MSB_A_VECM_INITZ_MASK ((uint8_t) 0x3F)
2948#define FXOS8700_A_VECM_INITZ_MSB_A_VECM_INITZ_SHIFT ((uint8_t) 0)
2949
2950
2951/*------------------------------*/
2952
2953
2954
2955/*--------------------------------
2956** Register: A_VECM_INITZ_LSB
2957** Enum: FXOS8700_A_VECM_INITZ_LSB
2958** --
2959** Offset : 0x68 - Acceleration vector magnitude Z-axis reference value LSB.
2960** ------------------------------*/
2961typedef uint8_t FXOS8700_A_VECM_INITZ_LSB_t;
2962
2963
2964/*--------------------------------
2965** Register: M_VECM_CFG
2966** Enum: FXOS8700_M_VECM_CFG
2967** --
2968** Offset : 0x69 - Magnetic vector magnitude configuration register.
2969** ------------------------------*/
2970typedef union {
2971 struct {
2972 uint8_t m_vecm_init_cfg : 1;
2973 uint8_t m_vecm_int_en : 1;
2974 uint8_t m_vecm_wake_en : 1;
2975 uint8_t a_vecm_en : 1;
2976 uint8_t m_vecm_updm : 1;
2977 uint8_t m_vecm_initm : 1;
2978 uint8_t m_vecm_ele : 1;
2979 uint8_t reserved : 1;
2980 } b;
2981 uint8_t w;
2982} FXOS8700_M_VECM_CFG_t;
2983
2984
2985/*
2986** M_VECM_CFG - Bit field mask definitions
2987*/
2988#define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_MASK ((uint8_t) 0x01)
2989#define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_SHIFT ((uint8_t) 0)
2990
2991#define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_MASK ((uint8_t) 0x02)
2992#define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_SHIFT ((uint8_t) 1)
2993
2994#define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_MASK ((uint8_t) 0x04)
2995#define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_SHIFT ((uint8_t) 2)
2996
2997#define FXOS8700_M_VECM_CFG_A_VECM_EN_MASK ((uint8_t) 0x08)
2998#define FXOS8700_M_VECM_CFG_A_VECM_EN_SHIFT ((uint8_t) 3)
2999
3000#define FXOS8700_M_VECM_CFG_M_VECM_UPDM_MASK ((uint8_t) 0x10)
3001#define FXOS8700_M_VECM_CFG_M_VECM_UPDM_SHIFT ((uint8_t) 4)
3002
3003#define FXOS8700_M_VECM_CFG_M_VECM_INITM_MASK ((uint8_t) 0x20)
3004#define FXOS8700_M_VECM_CFG_M_VECM_INITM_SHIFT ((uint8_t) 5)
3005
3006#define FXOS8700_M_VECM_CFG_M_VECM_ELE_MASK ((uint8_t) 0x40)
3007#define FXOS8700_M_VECM_CFG_M_VECM_ELE_SHIFT ((uint8_t) 6)
3008
3009#define FXOS8700_M_VECM_CFG_RESERVED_MASK ((uint8_t) 0x80)
3010#define FXOS8700_M_VECM_CFG_RESERVED_SHIFT ((uint8_t) 7)
3011
3012
3013/*
3014** M_VECM_CFG - Bit field value definitions
3015*/
3016#define FXOS8700_M_VECM_CFG_M_VECM_ELE_DIS ((uint8_t) 0x00) /* Event latch disabled */
3017#define FXOS8700_M_VECM_CFG_M_VECM_ELE_EN ((uint8_t) 0x40) /* Event latch enabled */
3018#define FXOS8700_M_VECM_CFG_M_VECM_INITM_OUT ((uint8_t) 0x00) /* The ASIC uses the current magnetic output data as */
3019 /* the initial reference values at the time the */
3020 /* m_vecm_en bit is set */
3021#define FXOS8700_M_VECM_CFG_M_VECM_INITM_STORED ((uint8_t) 0x20) /* The ASIC uses the data stored in the */
3022 /* M_VECM_X/Y/Z_INIT registers as the initial */
3023 /* reference values at the time the m_vecm_en bit is */
3024 /* set */
3025#define FXOS8700_M_VECM_CFG_M_VECM_UPDM_DIS ((uint8_t) 0x00) /* The function updates the reference values with */
3026 /* the current X, Y, and Z magnetic data when the */
3027 /* event is triggered */
3028#define FXOS8700_M_VECM_CFG_M_VECM_UPDM_EN ((uint8_t) 0x10) /* The function does not update the reference values */
3029 /* when the event is triggered */
3030#define FXOS8700_M_VECM_CFG_A_VECM_EN_EN ((uint8_t) 0x00) /* Function is disabled */
3031#define FXOS8700_M_VECM_CFG_A_VECM_EN_DIS ((uint8_t) 0x08) /* Function is enabled */
3032#define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_EN ((uint8_t) 0x00) /* The system excludes the src_m_vecm event flag */
3033 /* when evaluating the auto-sleep function */
3034#define FXOS8700_M_VECM_CFG_M_VECM_WAKE_EN_DIS ((uint8_t) 0x04) /* The system includes the src_m_vecm event flag */
3035 /* when evaluating the auto-sleep function */
3036#define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_EN ((uint8_t) 0x00) /* Magnetic vector-magnitude interrupt is disabled */
3037#define FXOS8700_M_VECM_CFG_M_VECM_INT_EN_DIS ((uint8_t) 0x02) /* Magnetic vector-magnitude interrupt is enabled */
3038#define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_INT2 ((uint8_t) 0x00) /* Magnetic vector-magnitude interrupt is output on */
3039 /* INT2 pin */
3040#define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_INT1 ((uint8_t) 0x01) /* Magnetic vector-magnitude interrupt is output on */
3041 /* INT1 pin. */
3042#define FXOS8700_M_VECM_CFG_M_VECM_INIT_CFG_DIS ((uint8_t) 0x01) /* Function is enabled */
3043/*------------------------------*/
3044
3045
3046
3047/*--------------------------------
3048** Register: M_VECM_THS_MSB
3049** Enum: FXOS8700_M_VECM_THS_MSB
3050** --
3051** Offset : 0x6A - Magnetic vector magnitude threshold MSB.
3052** ------------------------------*/
3053typedef union {
3054 struct {
3055 uint8_t m_vecm_ths : 7;
3056 } b;
3057 uint8_t w;
3058} FXOS8700_M_VECM_THS_MSB_t;
3059
3060
3061/*
3062** M_VECM_THS_MSB - Bit field mask definitions
3063*/
3064#define FXOS8700_M_VECM_THS_MSB_M_VECM_THS_MASK ((uint8_t) 0x7F)
3065#define FXOS8700_M_VECM_THS_MSB_M_VECM_THS_SHIFT ((uint8_t) 0)
3066
3067
3068/*------------------------------*/
3069
3070
3071
3072/*--------------------------------
3073** Register: M_VECM_THS_LSB
3074** Enum: FXOS8700_M_VECM_THS_LSB
3075** --
3076** Offset : 0x6B - Magnetic vector magnitude threshold LSB.
3077** ------------------------------*/
3078typedef uint8_t FXOS8700_M_VECM_THS_LSB_t;
3079
3080
3081/*--------------------------------
3082** Register: M_VECM_CNT
3083** Enum: FXOS8700_M_VECM_CNT
3084** --
3085** Offset : 0x6C - Magnetic vector magnitude debounce count.
3086** ------------------------------*/
3087typedef uint8_t FXOS8700_M_VECM_CNT_t;
3088
3089
3090/*--------------------------------
3091** Register: M_VECM_INITX_MSB
3092** Enum: FXOS8700_M_VECM_INITX_MSB
3093** --
3094** Offset : 0x6D - Magnetic vector magnitude X-axis reference value MSB.
3095** ------------------------------*/
3096typedef uint8_t FXOS8700_M_VECM_INITX_MSB_t;
3097
3098
3099/*--------------------------------
3100** Register: M_VECM_INITX_LSB
3101** Enum: FXOS8700_M_VECM_INITX_LSB
3102** --
3103** Offset : 0x6E - Magnetic vector magnitude X-axis reference value LSB.
3104** ------------------------------*/
3105typedef uint8_t FXOS8700_M_VECM_INITX_LSB_t;
3106
3107
3108/*--------------------------------
3109** Register: M_VECM_INITY_MSB
3110** Enum: FXOS8700_M_VECM_INITY_MSB
3111** --
3112** Offset : 0x6F - Magnetic vector magnitude Y-axis reference value MSB.
3113** ------------------------------*/
3114typedef uint8_t FXOS8700_M_VECM_INITY_MSB_t;
3115
3116
3117/*--------------------------------
3118** Register: M_VECM_INITY_LSB
3119** Enum: FXOS8700_M_VECM_INITY_LSB
3120** --
3121** Offset : 0x70 - Magnetic vector magnitude Y-axis reference value LSB.
3122** ------------------------------*/
3123typedef uint8_t FXOS8700_M_VECM_INITY_LSB_t;
3124
3125
3126/*--------------------------------
3127** Register: M_VECM_INITZ_MSB
3128** Enum: FXOS8700_M_VECM_INITZ_MSB
3129** --
3130** Offset : 0x71 - Magnetic vector magnitude Z-axis reference value MSB.
3131** ------------------------------*/
3132typedef uint8_t FXOS8700_M_VECM_INITZ_MSB_t;
3133
3134
3135/*--------------------------------
3136** Register: M_VECM_INITZ_LSB
3137** Enum: FXOS8700_M_VECM_INITZ_LSB
3138** --
3139** Offset : 0x72 - Magnetic vector magnitude Z-axis reference value LSB.
3140** ------------------------------*/
3141typedef uint8_t FXOS8700_M_VECM_INITZ_LSB_t;
3142
3143
3144/*--------------------------------
3145** Register: A_FFMT_THS_X_MSB
3146** Enum: FXOS8700_A_FFMT_THS_X_MSB
3147** --
3148** Offset : 0x73 - X-axis FFMT threshold MSB.
3149** ------------------------------*/
3150typedef uint8_t FXOS8700_A_FFMT_THS_X_MSB_t;
3151
3152
3153
3154/*--------------------------------
3155** Register: A_FFMT_THS_X_LSB
3156** Enum: FXOS8700_A_FFMT_THS_X_LSB
3157** --
3158** Offset : 0x74 - X-axis FFMT threshold LSB.
3159** ------------------------------*/
3160typedef union {
3161 struct {
3162 uint8_t a_ffmt_ths_x : 7;
3163 } b;
3164 uint8_t w;
3165} FXOS8700_A_FFMT_THS_X_LSB_t;
3166
3167
3168/*
3169** A_FFMT_THS_X_LSB - Bit field mask definitions
3170*/
3171#define FXOS8700_A_FFMT_THS_X_LSB_A_FFMT_THS_X_MASK ((uint8_t) 0x7F)
3172#define FXOS8700_A_FFMT_THS_X_LSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
3173
3174
3175/*------------------------------*/
3176
3177
3178
3179/*--------------------------------
3180** Register: A_FFMT_THS_Y_MSB
3181** Enum: FXOS8700_A_FFMT_THS_Y_MSB
3182** --
3183** Offset : 0x75 - Y-axis FFMT threshold MSB.
3184** ------------------------------*/
3185typedef uint8_t FXOS8700_A_FFMT_THS_Y_MSB_t;
3186
3187
3188/*--------------------------------
3189** Register: A_FFMT_THS_Y_LSB
3190** Enum: FXOS8700_A_FFMT_THS_Y_LSB
3191** --
3192** Offset : 0x76 - Y-axis FFMT threshold LSB.
3193** ------------------------------*/
3194typedef union {
3195 struct {
3196 uint8_t a_ffmt_ths_y : 7;
3197 } b;
3198 uint8_t w;
3199} FXOS8700_A_FFMT_THS_Y_LSB_t;
3200
3201
3202/*
3203** A_FFMT_THS_Y_LSB - Bit field mask definitions
3204*/
3205#define FXOS8700_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_MASK ((uint8_t) 0x7F)
3206#define FXOS8700_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_SHIFT ((uint8_t) 0)
3207
3208
3209/*------------------------------*/
3210
3211
3212
3213/*--------------------------------
3214** Register: A_FFMT_THS_Z_MSB
3215** Enum: FXOS8700_A_FFMT_THS_Z_MSB
3216** --
3217** Offset : 0x77 - Z-axis FFMT threshold MSB.
3218** ------------------------------*/
3219typedef uint8_t FXOS8700_A_FFMT_THS_Z_MSB_t;
3220
3221
3222/*--------------------------------
3223** Register: A_FFMT_THS_Z_LSB
3224** Enum: FXOS8700_A_FFMT_THS_Z_LSB
3225** --
3226** Offset : 0x78 - Z-axis FFMT threshold LSB.
3227** ------------------------------*/
3228typedef union {
3229 struct {
3230 uint8_t a_ffmt_ths_z : 7;
3231 } b;
3232 uint8_t w;
3233} FXOS8700_A_FFMT_THS_Z_LSB_t;
3234
3235
3236/*
3237** A_FFMT_THS_Z_LSB - Bit field mask definitions
3238*/
3239#define FXOS8700_A_FFMT_THS_Z_LSB_A_FFMT_THS_Z_MASK ((uint8_t) 0x7F)
3240#define FXOS8700_A_FFMT_THS_Z_LSB_A_FFMT_THS_Z_SHIFT ((uint8_t) 0)
3241
3242
3243/*------------------------------*/
3244
3245
3246#ifdef __cplusplus
3247}
3248#endif
3249
3250#endif /* DRIVER_FXOS8700_REGISTERS_H_ */
FXOS8700_MIN_Z_LSB
@ FXOS8700_MIN_Z_LSB
Definition driver_fxos8700_registers.h:99
FXOS8700_PULSE_TMLT
@ FXOS8700_PULSE_TMLT
Definition driver_fxos8700_registers.h:57
FXOS8700_OUT_Y_MSB
@ FXOS8700_OUT_Y_MSB
Definition driver_fxos8700_registers.h:28
FXOS8700_M_VECM_CFG
@ FXOS8700_M_VECM_CFG
Definition driver_fxos8700_registers.h:124
FXOS8700_STATUS
@ FXOS8700_STATUS
Definition driver_fxos8700_registers.h:25
FXOS8700_M_THS_Y_LSB
@ FXOS8700_M_THS_Y_LSB
Definition driver_fxos8700_registers.h:106
FXOS8700_A_FFMT_THS_X_LSB
@ FXOS8700_A_FFMT_THS_X_LSB
Definition driver_fxos8700_registers.h:135
FXOS8700_MIN_Y_MSB
@ FXOS8700_MIN_Y_MSB
Definition driver_fxos8700_registers.h:96
FXOS8700_M_VECM_INITZ_LSB
@ FXOS8700_M_VECM_INITZ_LSB
Definition driver_fxos8700_registers.h:133
FXOS8700_MIN_Z_MSB
@ FXOS8700_MIN_Z_MSB
Definition driver_fxos8700_registers.h:98
FXOS8700_PULSE_CFG
@ FXOS8700_PULSE_CFG
Definition driver_fxos8700_registers.h:52
FXOS8700_M_THS_Z_LSB
@ FXOS8700_M_THS_Z_LSB
Definition driver_fxos8700_registers.h:108
FXOS8700_PL_STATUS
@ FXOS8700_PL_STATUS
Definition driver_fxos8700_registers.h:39
FXOS8700_M_VECM_INITZ_MSB
@ FXOS8700_M_VECM_INITZ_MSB
Definition driver_fxos8700_registers.h:132
FXOS8700_A_VECM_INITZ_MSB
@ FXOS8700_A_VECM_INITZ_MSB
Definition driver_fxos8700_registers.h:122
FXOS8700_M_THS_Z_MSB
@ FXOS8700_M_THS_Z_MSB
Definition driver_fxos8700_registers.h:107
FXOS8700_M_OFF_X_LSB
@ FXOS8700_M_OFF_X_LSB
Definition driver_fxos8700_registers.h:83
FXOS8700_MAX_Z_MSB
@ FXOS8700_MAX_Z_MSB
Definition driver_fxos8700_registers.h:92
FXOS8700_F_SETUP
@ FXOS8700_F_SETUP
Definition driver_fxos8700_registers.h:32
FXOS8700_A_FFMT_THS_Y_LSB
@ FXOS8700_A_FFMT_THS_Y_LSB
Definition driver_fxos8700_registers.h:137
FXOS8700_CTRL_REG5
@ FXOS8700_CTRL_REG5
Definition driver_fxos8700_registers.h:65
FXOS8700_M_VECM_THS_MSB
@ FXOS8700_M_VECM_THS_MSB
Definition driver_fxos8700_registers.h:125
FXOS8700_A_FFMT_SRC
@ FXOS8700_A_FFMT_SRC
Definition driver_fxos8700_registers.h:45
FXOS8700_A_FFMT_COUNT
@ FXOS8700_A_FFMT_COUNT
Definition driver_fxos8700_registers.h:47
FXOS8700_M_THS_X_LSB
@ FXOS8700_M_THS_X_LSB
Definition driver_fxos8700_registers.h:104
FXOS8700_A_FFMT_CFG
@ FXOS8700_A_FFMT_CFG
Definition driver_fxos8700_registers.h:44
FXOS8700_PULSE_LTCY
@ FXOS8700_PULSE_LTCY
Definition driver_fxos8700_registers.h:58
FXOS8700_PULSE_THSZ
@ FXOS8700_PULSE_THSZ
Definition driver_fxos8700_registers.h:56
FXOS8700_M_DR_STATUS
@ FXOS8700_M_DR_STATUS
Definition driver_fxos8700_registers.h:69
FXOS8700_PL_BF_ZCOMP
@ FXOS8700_PL_BF_ZCOMP
Definition driver_fxos8700_registers.h:42
FXOS8700_PL_THS_REG
@ FXOS8700_PL_THS_REG
Definition driver_fxos8700_registers.h:43
FXOS8700_A_VECM_INITX_LSB
@ FXOS8700_A_VECM_INITX_LSB
Definition driver_fxos8700_registers.h:119
FXOS8700_MAX_Z_LSB
@ FXOS8700_MAX_Z_LSB
Definition driver_fxos8700_registers.h:93
FXOS8700_M_INT_SRC
@ FXOS8700_M_INT_SRC
Definition driver_fxos8700_registers.h:113
FXOS8700_TEMP
@ FXOS8700_TEMP
Definition driver_fxos8700_registers.h:100
FXOS8700_OUT_Y_LSB
@ FXOS8700_OUT_Y_LSB
Definition driver_fxos8700_registers.h:29
FXOS8700_A_VECM_CNT
@ FXOS8700_A_VECM_CNT
Definition driver_fxos8700_registers.h:117
FXOS8700_CTRL_REG4
@ FXOS8700_CTRL_REG4
Definition driver_fxos8700_registers.h:64
FXOS8700_A_VECM_CFG
@ FXOS8700_A_VECM_CFG
Definition driver_fxos8700_registers.h:114
FXOS8700_MAX_Y_MSB
@ FXOS8700_MAX_Y_MSB
Definition driver_fxos8700_registers.h:90
FXOS8700_TRIG_CFG
@ FXOS8700_TRIG_CFG
Definition driver_fxos8700_registers.h:33
FXOS8700_M_OUT_X_LSB
@ FXOS8700_M_OUT_X_LSB
Definition driver_fxos8700_registers.h:71
FXOS8700_CMP_Z_LSB
@ FXOS8700_CMP_Z_LSB
Definition driver_fxos8700_registers.h:81
FXOS8700_M_THS_CFG
@ FXOS8700_M_THS_CFG
Definition driver_fxos8700_registers.h:101
FXOS8700_CMP_X_LSB
@ FXOS8700_CMP_X_LSB
Definition driver_fxos8700_registers.h:77
FXOS8700_TRANSIENT_SRC
@ FXOS8700_TRANSIENT_SRC
Definition driver_fxos8700_registers.h:49
FXOS8700_CMP_X_MSB
@ FXOS8700_CMP_X_MSB
Definition driver_fxos8700_registers.h:76
FXOS8700_PULSE_WIND
@ FXOS8700_PULSE_WIND
Definition driver_fxos8700_registers.h:59
FXOS8700_M_THS_X_MSB
@ FXOS8700_M_THS_X_MSB
Definition driver_fxos8700_registers.h:103
FXOS8700_M_CTRL_REG1
@ FXOS8700_M_CTRL_REG1
Definition driver_fxos8700_registers.h:110
FXOS8700_XYZ_DATA_CFG
@ FXOS8700_XYZ_DATA_CFG
Definition driver_fxos8700_registers.h:37
FXOS8700_M_OFF_Z_LSB
@ FXOS8700_M_OFF_Z_LSB
Definition driver_fxos8700_registers.h:87
FXOS8700_PL_COUNT
@ FXOS8700_PL_COUNT
Definition driver_fxos8700_registers.h:41
FXOS8700_PL_CFG
@ FXOS8700_PL_CFG
Definition driver_fxos8700_registers.h:40
FXOS8700_MAX_X_LSB
@ FXOS8700_MAX_X_LSB
Definition driver_fxos8700_registers.h:89
FXOS8700_OFF_X
@ FXOS8700_OFF_X
Definition driver_fxos8700_registers.h:66
FXOS8700_A_VECM_THS_LSB
@ FXOS8700_A_VECM_THS_LSB
Definition driver_fxos8700_registers.h:116
FXOS8700_M_OUT_X_MSB
@ FXOS8700_M_OUT_X_MSB
Definition driver_fxos8700_registers.h:70
FXOS8700_M_OUT_Y_MSB
@ FXOS8700_M_OUT_Y_MSB
Definition driver_fxos8700_registers.h:72
FXOS8700_TRANSIENT_CFG
@ FXOS8700_TRANSIENT_CFG
Definition driver_fxos8700_registers.h:48
FXOS8700_M_OUT_Y_LSB
@ FXOS8700_M_OUT_Y_LSB
Definition driver_fxos8700_registers.h:73
FXOS8700_M_VECM_THS_LSB
@ FXOS8700_M_VECM_THS_LSB
Definition driver_fxos8700_registers.h:126
FXOS8700_M_VECM_INITY_LSB
@ FXOS8700_M_VECM_INITY_LSB
Definition driver_fxos8700_registers.h:131
FXOS8700_MIN_X_MSB
@ FXOS8700_MIN_X_MSB
Definition driver_fxos8700_registers.h:94
FXOS8700_M_VECM_INITX_LSB
@ FXOS8700_M_VECM_INITX_LSB
Definition driver_fxos8700_registers.h:129
FXOS8700_MAX_X_MSB
@ FXOS8700_MAX_X_MSB
Definition driver_fxos8700_registers.h:88
FXOS8700_MIN_Y_LSB
@ FXOS8700_MIN_Y_LSB
Definition driver_fxos8700_registers.h:97
FXOS8700_M_VECM_CNT
@ FXOS8700_M_VECM_CNT
Definition driver_fxos8700_registers.h:127
FXOS8700_A_FFMT_THS_Y_MSB
@ FXOS8700_A_FFMT_THS_Y_MSB
Definition driver_fxos8700_registers.h:136
FXOS8700_OUT_X_MSB
@ FXOS8700_OUT_X_MSB
Definition driver_fxos8700_registers.h:26
FXOS8700_M_VECM_INITY_MSB
@ FXOS8700_M_VECM_INITY_MSB
Definition driver_fxos8700_registers.h:130
FXOS8700_PULSE_THSX
@ FXOS8700_PULSE_THSX
Definition driver_fxos8700_registers.h:54
FXOS8700_TRANSIENT_COUNT
@ FXOS8700_TRANSIENT_COUNT
Definition driver_fxos8700_registers.h:51
FXOS8700_A_VECM_INITX_MSB
@ FXOS8700_A_VECM_INITX_MSB
Definition driver_fxos8700_registers.h:118
FXOS8700_M_OFF_Y_LSB
@ FXOS8700_M_OFF_Y_LSB
Definition driver_fxos8700_registers.h:85
FXOS8700_OUT_Z_MSB
@ FXOS8700_OUT_Z_MSB
Definition driver_fxos8700_registers.h:30
FXOS8700_MIN_X_LSB
@ FXOS8700_MIN_X_LSB
Definition driver_fxos8700_registers.h:95
FXOS8700_SYSMOD
@ FXOS8700_SYSMOD
Definition driver_fxos8700_registers.h:34
FXOS8700_CMP_Y_LSB
@ FXOS8700_CMP_Y_LSB
Definition driver_fxos8700_registers.h:79
FXOS8700_A_VECM_INITY_LSB
@ FXOS8700_A_VECM_INITY_LSB
Definition driver_fxos8700_registers.h:121
FXOS8700_CTRL_REG1
@ FXOS8700_CTRL_REG1
Definition driver_fxos8700_registers.h:61
FXOS8700_CTRL_REG3
@ FXOS8700_CTRL_REG3
Definition driver_fxos8700_registers.h:63
FXOS8700_A_FFMT_THS
@ FXOS8700_A_FFMT_THS
Definition driver_fxos8700_registers.h:46
FXOS8700_M_THS_Y_MSB
@ FXOS8700_M_THS_Y_MSB
Definition driver_fxos8700_registers.h:105
FXOS8700_ASLP_COUNT
@ FXOS8700_ASLP_COUNT
Definition driver_fxos8700_registers.h:60
FXOS8700_A_VECM_INITZ_LSB
@ FXOS8700_A_VECM_INITZ_LSB
Definition driver_fxos8700_registers.h:123
FXOS8700_CTRL_REG2
@ FXOS8700_CTRL_REG2
Definition driver_fxos8700_registers.h:62
FXOS8700_CMP_Y_MSB
@ FXOS8700_CMP_Y_MSB
Definition driver_fxos8700_registers.h:78
FXOS8700_A_FFMT_THS_Z_MSB
@ FXOS8700_A_FFMT_THS_Z_MSB
Definition driver_fxos8700_registers.h:138
FXOS8700_OUT_X_LSB
@ FXOS8700_OUT_X_LSB
Definition driver_fxos8700_registers.h:27
FXOS8700_CMP_Z_MSB
@ FXOS8700_CMP_Z_MSB
Definition driver_fxos8700_registers.h:80
FXOS8700_M_THS_SRC
@ FXOS8700_M_THS_SRC
Definition driver_fxos8700_registers.h:102
FXOS8700_M_OFF_Y_MSB
@ FXOS8700_M_OFF_Y_MSB
Definition driver_fxos8700_registers.h:84
FXOS8700_INT_SOURCE
@ FXOS8700_INT_SOURCE
Definition driver_fxos8700_registers.h:35
FXOS8700_M_CTRL_REG2
@ FXOS8700_M_CTRL_REG2
Definition driver_fxos8700_registers.h:111
FXOS8700_OUT_Z_LSB
@ FXOS8700_OUT_Z_LSB
Definition driver_fxos8700_registers.h:31
FXOS8700_A_VECM_INITY_MSB
@ FXOS8700_A_VECM_INITY_MSB
Definition driver_fxos8700_registers.h:120
FXOS8700_A_FFMT_THS_X_MSB
@ FXOS8700_A_FFMT_THS_X_MSB
Definition driver_fxos8700_registers.h:134
FXOS8700_PULSE_THSY
@ FXOS8700_PULSE_THSY
Definition driver_fxos8700_registers.h:55
FXOS8700_M_CTRL_REG3
@ FXOS8700_M_CTRL_REG3
Definition driver_fxos8700_registers.h:112
FXOS8700_MAX_Y_LSB
@ FXOS8700_MAX_Y_LSB
Definition driver_fxos8700_registers.h:91
FXOS8700_M_VECM_INITX_MSB
@ FXOS8700_M_VECM_INITX_MSB
Definition driver_fxos8700_registers.h:128
FXOS8700_HP_FILTER_CUTOFF
@ FXOS8700_HP_FILTER_CUTOFF
Definition driver_fxos8700_registers.h:38
FXOS8700_A_VECM_THS_MSB
@ FXOS8700_A_VECM_THS_MSB
Definition driver_fxos8700_registers.h:115
FXOS8700_OFF_Z
@ FXOS8700_OFF_Z
Definition driver_fxos8700_registers.h:68
FXOS8700_A_FFMT_THS_Z_LSB
@ FXOS8700_A_FFMT_THS_Z_LSB
Definition driver_fxos8700_registers.h:139
FXOS8700_WHO_AM_I
@ FXOS8700_WHO_AM_I
Definition driver_fxos8700_registers.h:36
FXOS8700_M_OUT_Z_LSB
@ FXOS8700_M_OUT_Z_LSB
Definition driver_fxos8700_registers.h:75
FXOS8700_OFF_Y
@ FXOS8700_OFF_Y
Definition driver_fxos8700_registers.h:67
FXOS8700_TRANSIENT_THS
@ FXOS8700_TRANSIENT_THS
Definition driver_fxos8700_registers.h:50
FXOS8700_PULSE_SRC
@ FXOS8700_PULSE_SRC
Definition driver_fxos8700_registers.h:53
FXOS8700_M_OFF_X_MSB
@ FXOS8700_M_OFF_X_MSB
Definition driver_fxos8700_registers.h:82
FXOS8700_M_THS_COUNT
@ FXOS8700_M_THS_COUNT
Definition driver_fxos8700_registers.h:109
FXOS8700_M_OUT_Z_MSB
@ FXOS8700_M_OUT_Z_MSB
Definition driver_fxos8700_registers.h:74
FXOS8700_M_OFF_Z_MSB
@ FXOS8700_M_OFF_Z_MSB
Definition driver_fxos8700_registers.h:86
FXOS8700_A_FFMT_CFG_t
Definition driver_fxos8700_registers.h:918
FXOS8700_A_FFMT_SRC_t
Definition driver_fxos8700_registers.h:976
FXOS8700_A_FFMT_THS_X_LSB_t
Definition driver_fxos8700_registers.h:3160
FXOS8700_A_FFMT_THS_Y_LSB_t
Definition driver_fxos8700_registers.h:3194
FXOS8700_A_FFMT_THS_Z_LSB_t
Definition driver_fxos8700_registers.h:3228
FXOS8700_A_FFMT_THS_t
Definition driver_fxos8700_registers.h:1026
FXOS8700_A_VECM_CFG_t
Definition driver_fxos8700_registers.h:2781
FXOS8700_A_VECM_INITX_MSB_t
Definition driver_fxos8700_registers.h:2868
FXOS8700_A_VECM_INITY_MSB_t
Definition driver_fxos8700_registers.h:2902
FXOS8700_A_VECM_INITZ_MSB_t
Definition driver_fxos8700_registers.h:2936
FXOS8700_A_VECM_THS_MSB_t
Definition driver_fxos8700_registers.h:2819
FXOS8700_CMP_X_MSB_t
Definition driver_fxos8700_registers.h:1979
FXOS8700_CMP_Y_MSB_t
Definition driver_fxos8700_registers.h:2013
FXOS8700_CMP_Z_MSB_t
Definition driver_fxos8700_registers.h:2047
FXOS8700_CTRL_REG1_t
Definition driver_fxos8700_registers.h:1485
FXOS8700_CTRL_REG2_t
Definition driver_fxos8700_registers.h:1557
FXOS8700_CTRL_REG3_t
Definition driver_fxos8700_registers.h:1616
FXOS8700_CTRL_REG4_t
Definition driver_fxos8700_registers.h:1698
FXOS8700_CTRL_REG5_t
Definition driver_fxos8700_registers.h:1771
FXOS8700_DR_STATUS_t
Definition driver_fxos8700_registers.h:164
FXOS8700_F_SETUP_t
Definition driver_fxos8700_registers.h:438
FXOS8700_F_STATUS_t
Definition driver_fxos8700_registers.h:237
FXOS8700_HP_FILTER_CUTOFF_t
Definition driver_fxos8700_registers.h:678
FXOS8700_INT_SOURCE_t
Definition driver_fxos8700_registers.h:575
FXOS8700_M_CTRL_REG1_t
Definition driver_fxos8700_registers.h:2535
FXOS8700_M_CTRL_REG2_t
Definition driver_fxos8700_registers.h:2612
FXOS8700_M_CTRL_REG3_t
Definition driver_fxos8700_registers.h:2687
FXOS8700_M_DR_STATUS_t
Definition driver_fxos8700_registers.h:1871
FXOS8700_M_INT_SRC_t
Definition driver_fxos8700_registers.h:2748
FXOS8700_M_OFF_X_LSB_t
Definition driver_fxos8700_registers.h:2090
FXOS8700_M_OFF_Y_LSB_t
Definition driver_fxos8700_registers.h:2125
FXOS8700_M_OFF_Z_LSB_t
Definition driver_fxos8700_registers.h:2160
FXOS8700_M_THS_CFG_t
Definition driver_fxos8700_registers.h:2320
FXOS8700_M_THS_SRC_t
Definition driver_fxos8700_registers.h:2373
FXOS8700_M_THS_X_MSB_t
Definition driver_fxos8700_registers.h:2423
FXOS8700_M_THS_Y_MSB_t
Definition driver_fxos8700_registers.h:2457
FXOS8700_M_THS_Z_MSB_t
Definition driver_fxos8700_registers.h:2491
FXOS8700_M_VECM_CFG_t
Definition driver_fxos8700_registers.h:2970
FXOS8700_M_VECM_THS_MSB_t
Definition driver_fxos8700_registers.h:3053
FXOS8700_OUT_X_LSB_t
Definition driver_fxos8700_registers.h:305
FXOS8700_OUT_X_MSB_t
Definition driver_fxos8700_registers.h:279
FXOS8700_OUT_Y_LSB_t
Definition driver_fxos8700_registers.h:358
FXOS8700_OUT_Y_MSB_t
Definition driver_fxos8700_registers.h:332
FXOS8700_OUT_Z_LSB_t
Definition driver_fxos8700_registers.h:411
FXOS8700_OUT_Z_MSB_t
Definition driver_fxos8700_registers.h:385
FXOS8700_PL_BF_ZCOMP_t
Definition driver_fxos8700_registers.h:823
FXOS8700_PL_CFG_t
Definition driver_fxos8700_registers.h:759
FXOS8700_PL_COUNT_t
Definition driver_fxos8700_registers.h:798
FXOS8700_PL_STATUS_t
Definition driver_fxos8700_registers.h:721
FXOS8700_PL_THS_REG_t
Definition driver_fxos8700_registers.h:868
FXOS8700_PULSE_CFG_t
Definition driver_fxos8700_registers.h:1233
FXOS8700_PULSE_SRC_t
Definition driver_fxos8700_registers.h:1318
FXOS8700_PULSE_THSX_t
Definition driver_fxos8700_registers.h:1371
FXOS8700_PULSE_THSY_t
Definition driver_fxos8700_registers.h:1396
FXOS8700_PULSE_THSZ_t
Definition driver_fxos8700_registers.h:1421
FXOS8700_SYSMOD_t
Definition driver_fxos8700_registers.h:535
FXOS8700_TEMP_t
Definition driver_fxos8700_registers.h:2295
FXOS8700_TRANSIENT_CFG_t
Definition driver_fxos8700_registers.h:1066
FXOS8700_TRANSIENT_SRC_t
Definition driver_fxos8700_registers.h:1134
FXOS8700_TRANSIENT_THS_t
Definition driver_fxos8700_registers.h:1183
FXOS8700_TRIG_CFG_t
Definition driver_fxos8700_registers.h:478
FXOS8700_XYZ_DATA_CFG_t
Definition driver_fxos8700_registers.h:638
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